PIC16F721-I/SO Microchip Technology, PIC16F721-I/SO Datasheet - Page 38

• Manufacturer Part Number: PIC16F721-I/SO
• Description: MCU PIC 4K FLASH 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-I/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 17
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Ram Memory Size: 256Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
4.1
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
• PEIE bit of the INTCON register (if the Interrupt
The INTCON and PIR1 registers record individual
interrupts via interrupt flag bits. Interrupt flag bits will be
set, regardless of the status of the GIE, PEIE and
individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated
FIGURE 4-2:
DS41430A-page 38
INSTRUCTION FLOW
event(s)
Enable bit of the interrupt event is contained in the
PIE1 register)
stack
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
Operation
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(3)
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
Q4
(5)
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
PC + 1
Q3
CY
. Synchronous latency = 3 T
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its Interrupt Flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
4.2
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See
for timing details.
PC + 1
—
Note 1: Individual interrupt flag bits are set,
Q3
Section 23.0 “Electrical
2: All interrupts will be ignored while the GIE
Interrupt Latency
Q4
(2)
CY
regardless of the state of any other
enable bits.
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
= instruction cycle time. Latency
Q3
 2010 Microchip Technology Inc.
Specifications”.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Figure 4-2
Q4