LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 229
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 11-29. IDDRFXA Symbol
Table 11-7 lists the port names and descriptions for the IDDRFXA primitive.
Table 11-7. IDDRFXA Port Names
Figure 11-31 shows the LatticeXP2 Input Register Block configured in the IDDRXFXA mode. CLK1 used to register
the DDR registers and the first set of synchronization registers. CLK2 is used by the third stage of registers and
should be clocked by the FPGA clock. These clock transfer registers are shared with the output register block.
Figure 11-30. Input Register Block configured as IDDRFXA
Figure 11-31 shows the timing waveform when using the IDDRFXA module.
DATA
D
CLK1
CLK2
CE
RST
QA
QB
Port Name
I/O
O
O
I
I
I
I
I
DDR Registers
B
A
DDR data
This clock can be connected to the ECLK or the FPGA clock
This clock should be connected to the FPGA clock
Clock Enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
D
CLK1
CLK2
CE
RST
C
Edge Clock
IDDRFXA
11-25
IDDRFXA
CLK1
Synchronization
QA
QB
Registers
Description
E
LatticeXP2 High-Speed I/O Interface
D
FPGA Clock
CLK2
Clock Transfer
Registers
H
I
QB
QA
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