LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 17
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-2. PFU Diagram
Slice
Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3
contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,
a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks
along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be com-
bined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset func-
tions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as posi-
tive/negative edge triggered or level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja-
cent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has
13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice
2.
Slice 0
Slice 1
Slice 2
Slice 3
Slice
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
FF
LUT4 &
CARRY
D
Slice 0
Resources
2 LUT4s
FF
LUT4 &
CARRY
D
PFU BLock
FF
LUT4 &
CARRY
D
Logic, Ripple, ROM
Slice 1
Logic, ROM
Modes
FF
LUT4 &
CARRY
D
Routing
Routing
From
2-3
To
FF
CARRY
LUT4 &
D
2 LUT4s and 2 Registers
Slice 2
Resources
2 LUT4s
FF
CARRY
LUT4 &
D
LatticeXP2 Family Data Sheet
PFF Block
LUT4
Slice 3
Logic, Ripple, ROM
Logic, Ripple, ROM
Logic, Ripple, ROM
Logic, ROM
LUT4
Modes
Architecture
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