LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 184
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 10-37. FIFO_DC with Output Registers, End of Data Read Cycle
And finally, if you select the option to enable the output register with RdEn, it still delays the data out by one clock
cycle (as compared to the non-pipelined FIFO_DC). The RdEn should also be high during that clock cycle, other-
wise the data takes an extra clock cycle when the RdEn is goes true.
Figure 10-38. FIFO_DC with Output Registers and RdEn on Output Registers
RPReset
RPReset
WrClock
RdClock
WrClock
RdClock
Almost
Almost
Almost
Almost
Empty
Empty
Empty
Empty
Reset
WrEn
RdEn
Reset
WrEn
RdEn
Data
Data
Full
Full
Full
Full
Q
Q
Data_N-4
Data_N-3
Invalid Q
10-34
Data_N-2
Invalid Data
Invalid Data
Data_1
Data_1
LatticeXP2 Memory Usage Guide
Data_N
Data_2
Data_3
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