AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 65
AFS600-PQG208
Manufacturer Part Number
AFS600-PQG208
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-PQG208
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
95
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AFS600-PQG208
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AFS600-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Figure 2-37 • FB Erase Page Waveform
OVERWRITEPROTECT
PAGELOSSPROTECT
STATUS[1:0]
ADDR[17:0]
Erase Page Operation
The Erase Page operation is initiated when the ERASEPAGE pin is asserted. The Erase Page operation
allows the user to erase (set user data to zero) any page within the FB.
The use of the OVERWRITEPAGE and PAGELOSSPROTECT pins is the same for erase as for a
Program Page operation.
As with the Program Page operation, a STATUS of '01' indicates that the addressed page is not erased.
A waveform for an Erase Page operation is shown in
Erase errors include the following:
ERASE
BUSY
1. Attempting to erase a page that is Overwrite Protected (STATUS = '01')
2. Attempting to erase a page that is not in the Page Buffer when the Page Buffer has entered Page
3. The Write Count of the erased page exceeding the Write Threshold defined in the part
4. The ECC Logic determining that there is an uncorrectable error within the erased page (STATUS
CLK
Loss Protection mode (STATUS = '01')
specification (STATUS = '11')
= '10')
Page
R e v i s i o n 1
Figure
2-37.
Actel Fusion Family of Mixed Signal FPGAs
Valid
2- 49
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