AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 50

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 34
Modes of Operation
Standby Mode
Standby mode allows periodic power-up and power-down of the FPGA fabric. In standby mode, the real-
time counter and crystal block are ON. The FPGA is not powered by disabling the 1.5 V voltage
regulator. The 1.5 V voltage regulator can be enabled when the preset count is matched. Refer to the
"Real-Time Counter (part of AB macro)" section
configured and enabled. Then VRPSM is shut off by deasserting the VRPU signal. The 1.5 V voltage
regulator is then disabled, and shuts off the 1.5 V output.
Sleep Mode
In sleep mode, the real-time counter and crystal blocks are OFF. The 1.5 V voltage regulator inside the
VRPSM can only be enabled by the PUB or TRST pin. Refer to the
System Monitor (VRPSM)" section on page 2-37
voltage regulator.
Standby and Sleep Mode Circuit Implementation
For extra power savings, VJTAG and VPP should be at the same voltage as VCC, floated or ground,
during standby and sleep modes. Note that when VJTAG is not powered, the 1.5 V voltage regulator
cannot be enabled through TRST.
VPP and VJTAG can control through an external switch. Actel recommends ADG839, ADG849, or
ADG841 as possible switches.
of the switch can be connected to PTBASE of the Fusion device. VJTAG can be controlled in same
manner.
Figure 2-28 • Implementation to Control VPP
Fusion
PTBASE
PTEM
Figure 2-28
3.3 V
shows the implementation for controlling VPP. The IN signal
R e visio n 1
for details. To enter standby mode, the RTC must be first
External
Pass
Transistor
2N2222
for details on power-up and power-down of the 1.5 V
1.5 V
VPP Supply
IN
S
ADG841
"Voltage Regulator and Power
VPP Pin of
Fusion