AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 49

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Real-Time Counter System
Note:
Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro)
XTLOSC
MODE[1:0]
FPGA_EN*
Real-Time Counter
AB
*Signals are hardwired internally and do not exist in the macro core.
Crystal Clock
RTCXTLSEL
XTAL1
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce
power consumption in many applications.
The RTC system is composed of five cores:
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during
standby mode.
SELMODE
•
•
•
•
•
•
•
XTL*
XTL
Sleep mode, typical 10 µA
Standby mode (RTC running), typical 3 mA with 20 MHz
RTC sub-block inside Analog Block (AB)
Voltage Regulator and Power System Monitor (VRPSM)
Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock
Resources chapter of the
Crystal clock; does not require instantiation in RTL
1.5 V voltage regulator; does not require instantiation in RTL
XTAL2
RTCXTLMODE[1:0]
RTC_MODE[1:0]
RTCPSMMATCH
RTCMATCH
Figure 2-27
RTCCLK
CLKOUT
shows their connection.
Can Be Route
to PLL
Fusion FPGA Fabric User’s Guide
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
PUB
R e v i s i o n 1
Power-Up/-Down
Toggle Control
Switch
TRST*
FPGAGOOD
PUCORE
VREN*
Actel Fusion Family of Mixed Signal FPGAs
1.5 Voltage Regulator
VREN*
for more detail.
External Pin
Internal Pin
Cores do not require any
RTL instantiation
Cores require RTL instantiation
Sub-block in cores does not
require additional RTL instantiation
PTBASE*
PTEM*
3.3 V
External
Pass
Transistor
2N2222
1.5 V
2- 33