AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 215

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-131 • Minimum and Maximum DC Input and Output Levels
Figure 2-121 • AC Loading
Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads
3.3 V PCI/PCI-X
Drive Strength
Per PCI
specification
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
0
Note:
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Data Path
*Measuring point = V
Test Point
3.3 V PCI, 3.3 V PCI-X
The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI
Bus applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path
characterization are described in
AC loadings are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is
described in
R = 25
Min.
Input High (V)
V
VIL
Table
3.3
R to VCCI for t
R to GND for t
trip
Max.
. See
V
2-132.
Table 2-87 on page 2-168
Min.
V
Measuring Point* (V)
0.285 * V
0.615 * V
VIH
DP
DP
Figure
(R)
Max.
(F)
V
CCI
CCI
Per PCI curves
2-121.
Enable Path
Test Point
for t
for t
Max.
R e v i s i o n 1
VOL
V
DP(R)
DP(F)
for a complete table of trip points.
R = 1 k
Min.
V
V
OH
VREF (typ.) (V)
mA
I
OL
10 pF for t
5 pF for t
R to VCCI for t
R to GND for t
Actel Fusion Family of Mixed Signal FPGAs
–
mA
I
OH
HZ
ZH
/ t
Max.
mA
I
/ t
OSL
LZ
HZ
LZ
ZHS
3
/ t
/ t
/ t
ZL
ZH
Max.
I
mA
OSH
C
ZL
/ t
/ t
LOAD
3
/ t
ZLS
ZHS
10
ZLS
µA
I
10
IL
(pF)
1
4
µA
I
2- 199
10
IH
2
4