ATMEGA32M1-AUR Atmel, ATMEGA32M1-AUR Datasheet - Page 61
![IC MPU AVR 32K 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AUR
Manufacturer Part Number
ATMEGA32M1-AUR
Description
IC MPU AVR 32K 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
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12.2.3
12.2.4
8209D–AVR–11/10
EIFR – External Interrupt Flag Register
PCICR – Pin Change Interrupt Control Register
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3:0 – INTF[3:0]: External Interrupt Flag 3:0
When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit INT3:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT3:0 are configured as a level interrupt.
• Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 - PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT26:24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3
Interrupt Vector. PCINT26:24 pins are enabled individually by the PCMSK3 Register.
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT14:8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT14:8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
R
6
–
0
6
–
0
R
5
–
0
R
5
–
0
R
R
4
–
0
4
–
0
ATmega16M1/32M1/64M1
INTF3
PCIE3
R/W
3
0
R
3
0
INTF2
PCIE2
R/W
R/W
2
0
2
0
INTF1
PCIE1
R/W
R/W
1
0
1
0
INTF0
PCIE0
R/W
R/W
0
0
0
0
PCICR
EIFR
61
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