ATMEGA32M1-AUR Atmel, ATMEGA32M1-AUR Datasheet - Page 216
![IC MPU AVR 32K 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AUR
Manufacturer Part Number
ATMEGA32M1-AUR
Description
IC MPU AVR 32K 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
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20.6
20.6.1
216
Register Description
ATmega16M1/32M1/64M1
LINCR – LIN Control Register
Note:
• Bit 7 - LSWRES: Software Reset
• Bit 6 - LIN13: LIN 1.3 mode
• Bit 5:4 - LCONF[1:0]: Configuration
The configuration settings for LIN and UART mode are shown in
Table 20-5.
Note:
Table 20-6.
Note:
Bit
Read/Write
Initial Value
LCONF[1:0]
00
01
10
11
LCONF[1:0]
00
01
10
11
10. LINDAT:
(1)
(1)
- All bits are in R/W accessible
- Note that LAINC has no more effect on the auto-incrementation and the access to the
full FIFO is done setting LINDX[2..0] of LINSEL
– 0 = No action
– 1 = Software reset (this bit is self-reset at the end of the reset procedure)
– 0 = LIN 2.1 (default)
– 1 = LIN 1.3
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted
1. Default
1. Default
LSWRES
LIN Mode Configuration
UART Mode Configuration
R/W
Mode
LIN Standard configuration (listen mode “off”, CRC “on” & Frame_Time_Out
“on”
No CRC, no Time out (listen mode “off”)
No Frame_Time_Out (listen mode “off” & CRC “on”)
Listening mode (CRC “on” & Frame_Time_Out “on”)
Mode
8-bit, no parity (listen mode “off”)
8-bit, even parity (listen mode “off”)
10 = 8-bit, odd parity (listen mode “off”)
Listening mode, 8-bit, no parity
7
0
LIN13
R/W
6
0
LCONF1
R/W
5
0
LCONF0
R/W
4
0
LENA
R
3
0
LCMD2
R/W
2
0
Table 20-5
LCMD1
R/W
1
0
and
LCMD0
R/W
0
0
Table
8209D–AVR–11/10
20-6.
LINCR
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