ATMEGA32M1-AUR Atmel, ATMEGA32M1-AUR Datasheet - Page 188
![IC MPU AVR 32K 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AUR
Manufacturer Part Number
ATMEGA32M1-AUR
Description
IC MPU AVR 32K 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
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19.10.10 CANBT3 – CAN Bit Timing Register 3
19.10.11 CANTCON – CAN Timer Control Register
188
ATmega16M1/32M1/64M1
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT3 is written.
• Bit 6:4 – PHS2[2:0]: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2:0] shall be ≥1 and ≤PHS1[2..0] (c.f.
“CAN Bit Timing” on page 165
• Bit 3:1 – PHS1[2:0]: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ =
If BRP = 0, SMP must be cleared.
• Bit 7:0 – TPRSC[7:0]: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
T
clk
Read/Write
Initial Value
Read/Write
Initial Value
CANTIM
– 0 - the sampling will occur once at the user configured sampling point - SP
– 1 - with three-point sampling configuration the first sampling will occur two
Bit
Bit
clocks before the user configured sampling point - SP, again at one
before SP and finally at SP. Then the bit level will be determined by a majority vote of
the three samples
=
T
TPRSC7
clk
R/W
7
7
0
-
-
-
IO
× 8 × (CANTCON [7:0] + 1)
TPRSC6
PHS22
R/W
R/W
6
0
6
0
and
TPRSC5
PHS21
R/W
R/W
Section 19.5.3 “Baud Rate” on page
5
0
5
0
Tphs2 = Tscl × (PHS2 [2:0] + 1)
Tphs1 = Tscl × (PHS1 [2:0] + 1)
TPRSC4
PHS20
R/W
R/W
4
0
4
0
TPRSC3
PHS12
R/W
R/W
3
0
3
0
TPRSC2
PHS11
R/W
R/W
2
0
2
0
TRPSC1
PHS10
R/W
R/W
1
0
1
0
172).
T
clk
T
clk
IO
TPRSC0
SMP
.
R/W
R/W
IO
0
0
0
0
Section 19.3.3
clock
8209D–AVR–11/10
T
clk
IO
CANTCON
CANBT3
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