ATMEGA325A-AUR Atmel, ATMEGA325A-AUR Datasheet - Page 74

• Manufacturer Part Number: ATMEGA325A-AUR
• Description: IC MCU AVR 32K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3
74
Alternate Port Functions
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 13-5. Alternate Port Functions
Note:
Table 13-2 on page 75
indexes from
signals are generated internally in the modules having the alternate function.
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
PTOExn:
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Figure 13-5 on page 74
summarizes the function of the overriding signals. The pin and port
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
DDOExn
DDOVxn
(1)
are not shown in the succeeding tables. The overriding
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
clk
DIxn:
AIOxn:
SYNCHRONIZER
WPx:
D
L
I/O
SET
CLR
:
Q
Q
WRITE DDRx
WRITE PORTx
PULLUP DISABLE
READ DDRx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
D
PINxn
CLR
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
Figure 13-2
CLR
CLR
D
D
1
0
clk
PUD
WDx
RDx
RRx
DIxn
AIOxn
RPx
I/O
can be overridden by
WRx
8285B–AVR–03/11
Figure 13-5
PTOExn
WPx
I/O
,