ATMEGA325-16MUR Atmel, ATMEGA325-16MUR Datasheet
ATMEGA325-16MUR
Specifications of ATMEGA325-16MUR
Related parts for ATMEGA325-16MUR
ATMEGA325-16MUR Summary of contents
Page 1
... Fully Static Operation – 16MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega325/ATmega3250) • 64KBytes (ATmega645/ATmega6450) – EEPROM • 1Kbytes (ATmega325/ATmega3250) • 2Kbytes (ATmega645/ATmega6450) – Internal SRAM • ...
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... Pin Configurations Figure 1-1. Pinout ATmega3250/6450 1 DNC 2 (RXD/PCINT0) PE0 3 (TXD/PCINT1) PE1 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 10 VCC 11 GND 12 DNC 13 (PCINT24) PJ0 (PCINT25) PJ1 14 15 DNC 16 DNC 17 DNC 18 DNC 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 ...
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... Figure 1-2. Pinout ATmega325/645 DNC 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: 2570M–AVR–04/11 INDEX CORNER ...
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... Overview The Atmel ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... Self-Programmable Flash on a monolithic chip, the Atmel Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega325/3250/645/6450 is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports ATmega325/3250/645/6450 as listed on 2.3.5 Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability ...
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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250/6450 as listed on page 72. ...
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... AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. 2570M–AVR–04/11 ATmega325/3250/645/6450 , even if the ADC is not used. If the ADC is used, it should be connected ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2570M–AVR–04/11 1. ATmega325/3250/645/6450 9 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 2570M–AVR–04/11 ATmega325/3250/645/6450 ® ® AVR core architecture in general ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel ATmega325/3250/645/6450 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2 on page 13, each register is also assigned a data memory address, ATmega325/3250/645/6450 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 6-4 on page 15 by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin- 2570M–AVR–04/11 ATmega325/3250/645/6450 The X-, Y-, and Z-registers R27 (0x1B) ...
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... Register File single clock Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. “Boot Loader Support – Read-While-Write Self-Programming” on page ATmega325/3250/645/6450 “Memory Program- “Interrupts” on page “Interrupts” on page 49 for more information. ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2570M–AVR–04/11 ATmega325/3250/645/6450 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) 16 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2570M–AVR–04/11 ATmega325/3250/645/6450 ; set Global Interrupt Enable 17 ...
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... AVR Memories This section describes the different memories in the Atmel ATmega325/3250/645/6450. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the Atmel ATmega325/3250/645/6450 features an EEPROM Memory for data storage. All three memory spaces are linear. ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048 bytes of internal data SRAM in the Atmel ATmega325/3250/645/6450 are all accessi- ble through all these addressing modes. The Register File is described in Register File” ...
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... Figure 7-3. 7.3 EEPROM Data Memory The Atmel ATmega325/3250/645/6450 contains 1/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis- ters, the EEPROM Data Register, and the EEPROM Control Register ...
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... The I/O space definition of the Atmel ATmega325/3250/645/6450 is shown in mary” on page All Atmel ATmega325/3250/645/6450 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Read/Write Initial Value • Bits 15:11 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bits 10:0 – EEAR10:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1/2K bytes EEPROM space ...
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... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. 2570M–AVR–04/11 ATmega325/3250/645/6450 for details about Boot Table 7-1 lists the typical pro- “ ...
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... EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega325/3250/645/6450 Typical Programming Time 3.4ms 24 ...
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... Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATmega325/3250/645/6450 LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 GPIOR1 GPIOR0 ...
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... I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External Clock Oscillator is halted, enabling USI start condition detection in all sleep modes. I/O ATmega325/3250/645/6450 35. The clock systems are detailed below. CPU Core RAM clk CPU clk FLASH Reset Logic Watchdog Timer Source clock ...
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... For all fuses “1” means unprogrammed while “0” means programmed. 27. The frequency of the Watchdog Oscillator is voltage dependent as shown in 306. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out (V CC 4.1ms 65ms ATmega325/3250/645/6450 (Note:) CKSEL3..0 1111 - 1000 0111 - 0110 0010 0000 0011, 0001, 0101, 0100 = 3.0V) ...
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... Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1:0 Power-save (1) 00 258 CK (1) 01 258 CK ( ATmega325/3250/645/6450 Figure 8-2 on page 28. Either a quartz 28. For ceramic resonators, the capacitor val- XTAL2 XTAL1 GND Table 8-3 on page Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 1K CK 32K CK This option should only be used if frequency stability at start-up is not important for the application for more details. ATmega325/3250/645/6450 Additional Delay from Reset Recommended (V = 5.0V) Usage CC 14CK + 4 ...
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... The device is shipped with this option selected. 31. To run the device on an external clock, the CKSEL Fuses must be programmed Table 8-9 on page 30). Crystal Oscillator Clock Frequency Frequency Range 0 - 16MHz ATmega325/3250/645/6450 “OSCCAL – Oscillator Calibration Register” on Table 27-2 on page 268. (1)(3) CKSEL3..0 0010 ...
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... CKOUT Fuse is programmed. 8.8 Timer/Counter Oscillator Atmel ATmega325/3250/645/6450 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized for use with a 32 ...
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... System Clock Prescaler The Atmel ATmega325/3250/645/6450 system clock can be divided by setting the Clock Prescale Register” on page when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 8-11. CLKPS3 2570M–AVR–04/11 ATmega325/3250/645/6450 CLKPCE – – – CLKPS3 R/W ...
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... Table 8-11. CLKPS3 2570M–AVR–04/11 ATmega325/3250/645/6450 Clock Prescaler Select CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 34 ...
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... The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. 9.1 Sleep Modes ATmega325/3250/645/6450, and their distribution. The figure is helpful in selecting an appropri- ate sleep mode. sources. Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. ...
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... If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2. 2570M–AVR–04/11 ATmega325/3250/645/6450 , clk , and clk , while allowing the other clocks to run. ...
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... The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections 2570M–AVR–04/11 ATmega325/3250/645/6450 “PRR – Power Reduction Register” on page “Analog Comparator” on page 197 “Analog to Digital Converter” on page 201 for details on how to configure the Analog “ ...
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... Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 2570M–AVR–04/11 ATmega325/3250/645/6450 for details on the start-up time. “Watchdog Timer” on page 45 for details on how to configure the Watchdog Timer. ...
Page 39
... Sleep Mode Select SM1 SM0 Standby mode is only recommended for use with external crystals or resonators. ATmega325/3250/645/6450 SM2 SM1 SM0 SE R/W R/W R/W R Table 9-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby Reserved SMCR 39 ...
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... Read/Write Initial Value • Bits 7:4 - Reserved bits These bits are reserved bits in Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is enabled, operation will continue like before the shutdown. ...
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... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 10.2 Reset Sources The Atmel ATmega325/3250/645/6450 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega325/3250/645/6450 DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 301. The POR is activated whenever CC 42 ...
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... Figure 10-4. External Reset During Operation 10.5 Brown-out Detection Atmel ATmega325/3250/645/6450 has an On-chip Brown-out Detection (BOD) circuit for moni- toring the V the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as ...
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... Figure 10-6. Watchdog Reset During Operation 10.7 Internal Voltage Reference Atmel ATmega325/3250/645/6450 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the Atmel ATmega325/3250/645/6450 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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... WDTCR, r16 ret (1) /* Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See “About Code Examples” on page ATmega325/3250/645/6450 Typical Time-out Typical Time-out 3. 5. 17.1ms 16.3ms 34.3ms 32 ...
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... This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. 2570M–AVR–04/11 ATmega325/3250/645/6450 – ...
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... Read/Write Initial Value • Bits 7:5 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATmega325/3250/645/6450. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11.1 Interrupt Vectors in Atmel ATmega325/3250/645/6450 Table 11-1. Vector No (3) 24 (3) 25 Note: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see port – ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel ATmega325/3250/645/6450 is: Addre ss 0x000 0 0x000 2 0x000 4 0x000 ...
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... A 0x002 C 0x002 E 0x003 0 ; 0x003 2 0x003 3 0x003 4 0x003 5 0x003 6 0x003 7 2570M–AVR–04/11 ATmega325/3250/645/6450 jmp USI_OVF jmp ANA_COMP jmp ADC jmp EE_RDY jmp SPM_RDY ;NOT_USED jmp PCINT2 jmp PCINT3 RESET ldi r16, : high(RAMEND) out SPH,r16 ldi r16, low(RAMEND) out ...
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... Address Labels Code .org 0x0002 0x0002 0x0004 ... 0x002C ; .org 0x3800/0x7800 0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start 0x3801/0x7801 0x3802/0x7802 0x3803/0x7803 0x3804/0x7804 0x3805/0x7805 2570M–AVR–04/11 ATmega325/3250/645/6450 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx jmp EXT_INT0 jmp PCINT0 ...
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... To avoid unintentional changes of Interrupt Vector If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed ATmega325/3250/645/6450 Comments ; Reset handler ; IRQ0 Handler ; PCINT0 Handler ...
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... MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret /* Enable change of Interrupt Vectors */ MCUCR |= (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR |= (1<<IVSEL); ATmega325/3250/645/6450 “Boot Loader Support – Read-While- for details on Boot Lock bits. 54 ...
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... The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 12.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in 2570M–AVR–04/11 ATmega325/3250/645/6450 “Clock Systems and their Distribution” on page 26. Figure 12-1. 26. Low 55 ...
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... The value on the INT0 pin is sampled before detecting Interrupt 0 Sense Control ISC00 Description 0 The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request. ATmega325/3250/645/6450 pcint_in_(0) 0 pcint_syn pcint_setflag x clk – ...
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... The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3 Interrupt Vector. PCINT30..24 pins are enabled individually by the PCMSK3 Register. This bit is reserved bit in ATmega325/645 and should always be written to zero. • Bit 6 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
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... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. This bit is reserved bit in ATmega325/645 and will always be read as zero. • Bit 6– PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2 becomes set (one) ...
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... Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 2570M–AVR–04/11 1. PCMSK3 and PCMSK2 are only present in ATmega3250/6450 ...
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... Using the I/O port as General Digital I/O is described in 61. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 13-1. Refer to Pxn ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 81, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega325/3250/645/6450 Figure 13-2 PUD Q D ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 13-2, the PINxn Register bit and the preceding latch con- pd,max ATmega325/3250/645/6450 Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 13-3 ...
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... Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS 2570M–AVR–04/11 SYSTEM CLK XXX SYNC LATCH PINxn r17 ATmega325/3250/645/6450 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF 63 ...
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... Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega325/3250/645/6450 0xFF nop in r17, PINx 0x00 t pd 0xFF 64 ...
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... Figure 13-2, the digital input signal can be clamped to ground at the input of the “Alternate Port Functions” on page ATmega325/3250/645/6450 /2. CC 66. 65 ...
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... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega325/3250/645/6450 Figure 13-2 can be overridden by ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate Input/Output functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega325/3250/645/6450 Fig- 67 ...
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... The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source. 2570M–AVR–04/11 ATmega325/3250/645/6450 Port B Pins Alternate Functions Alternate Functions OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt15) ...
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... When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. 2570M–AVR–04/11 ATmega325/3250/645/6450 69 ...
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... SPI SLAVE SPI MSTR OUTPUT OUTPUT – – PCINT11 • PCINT10 • PCIE1 PCIE1 1 1 PCINT11 INPUT PCINT10 INPUT SPI MSTR SPI SLAVE INPUT INPUT – – ATmega325/3250/645/6450 PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE OC1A OC0A – – PCINT13 • ...
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... Port D to the overriding signals shown in 66. Overriding Signals for Alternate Functions in PD3:PD0 PD3 PD2 – – – – – – ATmega325/3250/645/6450 Table 13-6. PD1/INT0 PD0/ICP1 – – INT0 ENABLE 0 INT0 ENABLE 0 INT0 INPUT ICP1 INPUT – – ...
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... AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source. 2570M–AVR–04/11 ATmega325/3250/645/6450 Port E Pins Alternate Functions Alternate Function PCINT7 (Pin Change Interrupt7) ...
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... WIRE clk DO I/O – – PCINT7 • PCIE0 PCINT6 • PCIE0 1 1 PCINT7 INPUT PCINT6 INPUT – – 1. CKOUT is one if the CKOUT Fuse is programmed ATmega325/3250/645/6450 PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE 0 0 USI_TWO-WIRE USI_TWO-WIRE (SDA + (USI_SCL_HOL PORTE5) • PORTE4) • DDE5 ...
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... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega325/3250/645/6450 PE1/TXD/ PE0/RXD/PCINT PCINT1 0 TXEN RXEN 0 PORTE0 • ...
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... ADC3 - ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3-0. Table 13-12. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2570M–AVR–04/11 ATmega325/3250/645/6450 . . . PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 1 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN ...
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... RESET T0 (Timer/Counter0 Clock Inpu) T1 (Timer/Counter1 Clock Input Port G, PG5 is input only. Pull-up is always on. See Table 26-3 on page 266 for RSTDISBL fuse. and Table 13-15 relates the alternate functions of Port G to the overriding signals Figure 13-5 on page 66. ATmega325/3250/645/6450 PF1/ADC1 PF0/ADC0 – – ...
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... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.6 Alternate Functions of Port H Port H is only present in ATmega3250/6450. The alternate pin configuration is as follows: Table 13-16. Port H Pins Alternate Functions Port Pin PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 The alternate pin configuration is as follows: • ...
Page 78
... Port H to the overriding signals Figure 13-5 on page 66. PH7/PCINT23 PH6/PCINT22 – – PCINT23 • PCINT22 • PCIE0 PCIE0 0 0 PCINT23 INPUT PCINT22 INPUT – – ATmega325/3250/645/6450 PH5/PCINT21 PH4/PCINT20 – – PCINT21 • PCINT20 • PCIE0 PCIE0 0 0 PCINT21 INPUT PCINT20 INPUT – – 78 ...
Page 79
... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port J Port J is only present in ATmega3250/6450. The alternate pin configuration is as follows: Table 13-19. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin configuration is as follows: • ...
Page 80
... DIEOE DIEOV DI AIO 2570M–AVR–04/11 and Table 13-21 relates the alternate functions of Port J to the overriding signals Figure 13-5 on page 66. PJ6/PCINT30 – PCINT30 • PCIE0 0 – – ATmega325/3250/645/6450 PJ5/PCINT29 PJ4/PCINT28 – – PCINT29 • PCINT28 • PCIE0 PCIE0 0 0 – ...
Page 81
... Bit 0x02 (0x22) Read/Write Initial Value 13.4.3 DDRA – Port A Data Direction Register Bit 0x01 (0x21) Read/Write Initial Value 13.4.4 PINA – Port A Input Pins Address Bit 0x00 (0x20) Read/Write Initial Value 2570M–AVR–04/11 ATmega325/3250/645/6450 PJ3/PCINT27 PJ2/PCINT26 – – PCINT27 • ...
Page 82
... Read/Write Initial Value 13.4.11 PORTD – Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 13.4.12 DDRD – Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 2570M–AVR–04/11 ATmega325/3250/645/6450 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R ...
Page 83
... Initial Value 13.4.19 PINF – Port F Input Pins Address Bit 0x0F (0x2F) Read/Write Initial Value 13.4.20 PORTG – Port G Data Register Bit 0x14 (0x34) Read/Write Initial Value 2570M–AVR–04/11 ATmega325/3250/645/6450 PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A ...
Page 84
... R ( – DDJ6 DDJ5 DDJ4 R R/W R – PINJ6 PINJ5 PINJ4 R R/W R/W R/W 0 N/A N/A N/A 1. Register only available in ATmega3250/6450. ATmega325/3250/645/6450 DDG3 DDG2 DDG1 DDG0 R/W R/W R/W R PING3 PING2 PING1 PING0 R/W R/W R/W R/W N/A N/A N/A N PORTH3 PORTH2 ...
Page 85
... A. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. 2570M–AVR–04/11 ATmega325/3250/645/6450 “Pinout ATmega3250/6450” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are 96. TCCRn count ...
Page 86
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. for details. The compare match event will also set the Compare Flag “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega325/3250/645/6450 99 See “Output ...
Page 87
... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 90. ATmega325/3250/645/6450 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 88
... Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-3 Figure 14-3. Output Compare Unit, Block Diagram 2570M–AVR–04/11 ATmega325/3250/645/6450 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. DATA BUS OCRnx ...
Page 89
... PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin System Reset occur, the OC0A Register is reset to “0”. 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 14-4 shows a sim- 89 ...
Page 90
... COMnx1 Waveform COMnx0 Generator FOCn clk I/O See “Register Description” on page 96. Table 14-3 on page 97, and for phase correct PWM refer to (See “Compare Match Output Unit” on page Figure ATmega325/3250/645/6450 OCnx PORT D Q DDR 97. For fast PWM mode, refer to Table 14-5 on page 98 ...
Page 91
... For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 1 2 ...
Page 92
... Figure 14-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. 2570M–AVR–04/11 ATmega325/3250/645/6450 f clk_I ------------------------------------------------- - OCnx ⋅ ...
Page 93
... The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. 2570M–AVR–04/11 ATmega325/3250/645/6450 Table 14-4 on page f clk_I/O ...
Page 94
... TOM. There are two cases that give a transition without Compare Match. • OCR0A changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. 2570M–AVR–04/11 ATmega325/3250/645/6450 clk_I/O f ...
Page 95
... MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 ATmega325/3250/645/6450 ) is therefore shown MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value BOTTOM + 1 ...
Page 96
... OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - FOC0A WGM00 COM0A1 COM0A0 W R/W R/W R 90. ATmega325/3250/645/6450 TOP BOTTOM TOP WGM01 CS02 CS01 CS00 R/W R/W R/W R Table 14-2 and “Modes of Operation” ...
Page 97
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See for more details. shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor- ATmega325/3250/645/6450 (1) Update of TOV0 Flag ...
Page 98
... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCR0A[7:0] R/W R/W R/W R ATmega325/3250/645/6450 (1) “Phase Correct PWM Mode” R/W R/W R/W R R/W R/W R/W R TCNT0 OCR0 98 ...
Page 99
... PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. 15. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 2570M–AVR–04/11 ATmega325/3250/645/6450 – ...
Page 100
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega325/3250/645/6450 /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 1 ). The latch clk ...
Page 101
... Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2570M–AVR–04/11 I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( TSM – – R ATmega325/3250/645/6450 (1) T1 T1/T0) is shown in Figure – – – PSR2 PSR10 R/W R/W ...
Page 102
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in Timer/Counter1 module. 2570M–AVR–04/11 ATmega325/3250/645/6450 “Pinout ATmega3250/6450” on page “Register Description” on page “Power Reduction Register” on page 37 Figure 16-1. For the actual 2. CPU accessible I/O Reg- 123 ...
Page 103
... Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, “Alternate Functions of Port D” on page Functions of Port G” on page 76for Timer/Counter1 pin placement and description. ATmega325/3250/645/6450 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int ...
Page 104
... The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit 2570M–AVR–04/11 ATmega325/3250/645/6450 The compare match event will also set the Compare Match 197.) The Input Capture unit includes a digital filtering unit (Noise Definitions of Timer/Counter values ...
Page 105
... Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 105 ...
Page 106
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 106 ...
Page 107
... SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega325/3250/645/6450 9. 99. 107 ...
Page 108
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega325/3250/645/6450 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 114 ...
Page 109
... ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 2570M–AVR–04/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega325/3250/645/6450 Figure 16-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 110
... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 2570M–AVR–04/11 104. ATmega325/3250/645/6450 “Accessing 16-bit Registers” (Figure 1 on page 100). The edge detector is also ...
Page 111
... The double buffering synchronizes the update of the OCR1x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization 2570M–AVR–04/11 ATmega325/3250/645/6450 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 112
... Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. 2570M–AVR–04/11 104. ATmega325/3250/645/6450 “Accessing 16-bit Registers” 112 ...
Page 113
... OC1x Register performed on the next compare match. For compare output actions in the non-PWM modes refer to page 124, and for phase correct and phase and frequency correct PWM refer to page 124. 2570M–AVR–04/11 Waveform Generator I/O See “Register Description” on page 123. Table 16-2 on page ATmega325/3250/645/6450 Figure 16 OCnx PORT D Q ...
Page 114
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 2570M–AVR–04/11 ATmega325/3250/645/6450 112.) “Timer/Counter Timing Diagrams” on page Figure 16-6. The counter value (TCNT1) 121 ...
Page 115
... PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. 2570M–AVR–04/11 ATmega325/3250/645/6450 when OCR1A is set to zero (0x0000) ...
Page 116
... TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 2570M–AVR–04/11 ATmega325/3250/645/6450 ( TOP log ...
Page 117
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 2570M–AVR–04/11 ATmega325/3250/645/6450 Table 16-3 on page f clk_I/O f ...
Page 118
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This 2570M–AVR–04/11 ATmega325/3250/645/6450 ( ) TOP ...
Page 119
... OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 2570M–AVR–04/11 ATmega325/3250/645/6450 f OCnxPCPWM 16-9). Table 1 on page f clk_I/O ...
Page 120
... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 16-9 cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 2570M–AVR–04/11 ATmega325/3250/645/6450 log R = ---------------------------------- - PFCPWM Figure 16-9 ...
Page 121
... OCnxPFCPWM Figure 16-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega325/3250/645/6450 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value ...
Page 122
... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega325/3250/645/6450 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 123
... COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R Table 16-2 Compare Output Mode, non-PWM COM1A0/COM1B0 ATmega325/3250/645/6450 /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value – – WGM11 WGM10 R R R/W R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected ...
Page 124
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 117. Table 16-5. Modes of operation supported by the Timer/Counter ATmega325/3250/645/6450 (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 125
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega325/3250/645/6450 Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A BOTTOM ICR1 ...
Page 126
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R ATmega325/3250/645/6450 – – – – Figure TCCR1C 126 ...
Page 127
... CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value 2570M–AVR–04/11 ATmega325/3250/645/6450 TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R/W ...
Page 128
... TOV1 Flag, located in TIFR1, is set – – ICF1 – R ATmega325/3250/645/6450 – OCIE1B OCIE1A TOIE1 R R/W R/W R 49.) is executed when the OCF1B Flag, located in 49.) is executed when the OCF1A Flag, located in ...
Page 129
... TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 2570M–AVR–04/11 ATmega325/3250/645/6450 Table 16-5 on page 125 for the TOV1 129 ...
Page 130
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 17-1. 8-bit Timer/Counter Block Diagram 2570M–AVR–04/11 ATmega325/3250/645/6450 “Pinout ATmega3250/6450” on page “Register Description” on page TCCRnx count clear ...
Page 131
... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 shows a block diagram of the counter and its surrounding environment. 2570M–AVR–04/11 ATmega325/3250/645/6450 ). T2 for details. The compare match event will also set the Compare Table 17-1 are also used extensively throughout the section. ...
Page 132
... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 135. 135). shows a block diagram of the Output Compare unit. ATmega325/3250/645/6450 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top TOSC1 ...
Page 133
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is counting down. 2570M–AVR–04/11 ATmega325/3250/645/6450 DATA BUS OCRnx = (8-bit Comparator ) ...
Page 134
... The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. 2570M–AVR–04/11 Waveform Generator clk I/O See “Register Description” on page 143. ATmega325/3250/645/6450 Figure 17 OCnx ...
Page 135
... Table 17-3 on page 144, and for phase correct PWM refer to (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ATmega325/3250/645/6450 144. For fast PWM mode, refer to Table 17-5 on page 144. 134.). Figure 17-5. The counter value (TCNT2) Table 17-4 139 ...
Page 136
... In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
Page 137
... OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 17-6. The TCNT2 value is in the timing diagram shown as a his- 1 ...
Page 138
... The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 17-7 ...
Page 139
... I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. ATmega325/3250/645/6450 f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 17-7. When the OCR2A value is MAX the should be replaced by I/O ...
Page 140
... OCRnx OCFnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega325/3250/645/6450 /8) clk_I/O MAX BOTTOM BOTTOM + 1 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP /8) clk_I/O OCRnx + 2 140 ...
Page 141
... When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four 2570M–AVR–04/11 ATmega325/3250/645/6450 141 ...
Page 142
... TCNT2 will read as the previous I/O clk clk I/O T2S Clear AS2 PSR2 CS20 CS21 CS22 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO ATmega325/3250/645/6450 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S 142 ...
Page 143
... Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega325/3250/645/6450 /8, clk T2S T2S as well as 0 (stop) may be selected. T2S ...
Page 144
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 138 for more details. ATmega325/3250/645/6450 (1) “Fast PWM Mode” on (1) “Phase Correct PWM Mode” on ...
Page 145
... Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. 2570M–AVR–04/11 ATmega325/3250/645/6450 Clock Select Bit Description CS21 CS20 ...
Page 146
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 2570M–AVR–04/11 ATmega325/3250/645/6450 – ...
Page 147
... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 101 2570M–AVR–04/11 ATmega325/3250/645/6450 – ...
Page 148
... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel ATmega325/3250/645/6450 and peripheral devices or between several AVR devices. The PRSPI bit in SPI module. Figure 18-1. SPI Block Diagram Note: 2570M– ...
Page 149
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure SHIFT ENABLE 18-2. The sys- ...
Page 150
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 68 direction of the user defined SPI pins. ATmega325/3250/645/6450 Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the “Alternate Port 150 ...
Page 151
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 151 ...
Page 152
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 152 ...
Page 153
... Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 18-4, as done below: CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) ATmega325/3250/645/6450 Trailing eDge SPI Mode Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Figure 0 1 ...
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... CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit SPIE SPE DORD MSTR R/W R/W R/W R ATmega325/3250/645/6450 Bit 4 Bit 3 Bit 2 Bit 1 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit CPOL CPHA ...
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... CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup Relationship Between SCK and the Oscillator Frequency SPR1 SPR0 ATmega325/3250/645/6450 for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-4 for an example. The CPOL Trailing Edge Setup Sample SCK Frequency osc osc ...
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... WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5:1 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit ...
Page 157
... A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. The Power Reduction USART bit, PRUSART0 written to zero to enable the USART0 module. 2570M–AVR–04/11 ATmega325/3250/645/6450 Figure 19-1. CPU accessible “Power Reduction Register” on page 37 must ...
Page 158
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Figure 1-2 on page 3 page 72 for USART pin placement. ATmega325/3250/645/6450 Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...
Page 159
... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 19-2 2570M–AVR–04/11 ATmega325/3250/645/6450 shows a block diagram of the clock generation logic. Figure 19-1) if the Buffer Registers ...
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... Input from XCK pin (internal Signal). Used for synchronous slave Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculat- ATmega325/3250/645/6450 U2X / ...
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... Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRH and UBRRL Registers, (0-4095) 176). Figure 19-2 for details. depends on the stability of the system clock source therefore recommended to osc ATmega325/3250/645/6450 Equation for Calculating (1) UBRR Value f f OSC OSC ...
Page 162
... Figure 19-4 optional. 2570M–AVR–04/11 UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 19-3 shows, when UCPOLn is zero the data will be changed illustrates the possible combinations of the frame formats. Bits inside brackets are ATmega325/3250/645/6450 Sample Sample 162 ...
Page 163
... No transfers on the communication line (RxD or TxD). An IDLE line must high. ⊕ even n 1 – ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega325/3250/645/6450 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
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... USART_Init(MYUBRR) ... /* Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ0); 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 164 ...
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... UCSR0A,UDRE0 rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 165 ...
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... Put data into buffer, sends the data */ UDR0 = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is used after initialization. 2. See “About Code Examples” on page ATmega325/3250/645/6450 9. 166 ...
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... Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. 2570M–AVR–04/11 ATmega325/3250/645/6450 167 ...
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... UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret (1) /* Wait for data to be received */ while ( !(UCSR0A & (1<<RXC0 Get and return received data from buffer */ return UDR0; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 168 ...
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... UCSR0A; resh = UCSR0B; resl = UDR0 error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. 169 ...
Page 170
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 2570M–AVR–04/11 ATmega325/3250/645/6450 “Parity Bit Calculation” on page 163 and “Parity Checker” on page 170 ...
Page 171
... RxD line is idle (i.e., no communication activity). 2570M–AVR–04/11 (1) sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush (1) unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; 1. See “About Code Examples” on page ATmega325/3250/645/6450 9. Figure 19-5 171 ...
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... RxD IDLE Sample (U2X = Sample (U2X = RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega325/3250/645/6450 START Figure 19-6 shows the sampling of the data bits and BIT ...
Page 173
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 19-3 list the maximum receiver baud rate error that can be tolerated. Note ATmega325/3250/645/6450 STOP 1 (A) ( ...
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... ATmega325/3250/645/6450 Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± 1.5 ...
Page 175
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 2570M–AVR–04/11 ATmega325/3250/645/6450 175 ...
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... ATmega325/3250/645/6450 Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRR Error UBRR Error 95 0. ...
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... Max. 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% 2570M–AVR–04/11 ATmega325/3250/645/6450 f = 4.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0. ...
Page 178
... Mbps 691.2 kbps ATmega325/3250/645/6450 MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 179
... Mbps 1.152 Mbps RXB[7:0] TXB[7:0] R/W R/W R/W R ATmega325/3250/645/6450 f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 ...
Page 180
... This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
Page 181
... Transmit Shift Register and Transmit Buffer Register do not contain data to be trans- mitted. When disabled, the Transmitter will no longer override the TxD port. 2570M–AVR–04/11 ATmega325/3250/645/6450 “Multi-processor Communication Mode” on page 7 6 ...
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... UMSELn UPMn1 UPMn0 R R/W R/W R UMSEL Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation UPM Bits Settings UPMn1 UPMn0 ATmega325/3250/645/6450 USBSn UCSZn1 UCSZn0 UCPOLn R/W R/W R/W R Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSRnC 182 ...
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... UCSZn2 UCSZn1 Transmitted Data Changed (Output of TxD Pin) 0 Rising XCK Edge 1 Falling XCK Edge ATmega325/3250/645/6450 Stop Bit(s) 1-bit 2-bit UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge ...
Page 184
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
Page 185
... The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate 2570M–AVR–04/11 ATmega325/3250/645/6450 “Pinout ATmega3250/6450” on page ...
Page 186
... USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 2570M–AVR–04/11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in Three-wire mode, one as Master and one as ATmega325/3250/645/6450 DO DI USCK DO DI USCK PORTxn 186 ...
Page 187
... The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: SPITransfer_loop: 2570M–AVR–04/11 ( Reference ) MSB MSB sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) sts USICR,r16 lds r16, USISR sbrs r16, USIOIF ATmega325/3250/645/6450 LSB LSB 8 E 187 ...
Page 188
... USICR,r16 ; MSB sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 ; LSB sts USICR,r17 lds r16,USIDR ATmega325/3250/645/6450 188 ...
Page 189
... Pin names used by this mode are SCL and SDA. 2570M–AVR–04/11 ldi r16,(1<<USIWM0)|(1<<USICS1) sts USICR,r16 sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 lds r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret ATmega325/3250/645/6450 189 ...
Page 190
... The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. Figure 20-5. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 20-5.), a bus transfer involves the following steps: 2570M–AVR–04/11 ATmega325/3250/645/6450 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 ...
Page 191
... Clock speed considerations. Maximum frequency for SCL and SCK is f receieve rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con- 2570M–AVR–04/11 ATmega325/3250/645/6450 SDA SCL Write( USISIF) “Clock Systems and their Distribution” on page /4. This is also the maximum data transmit and ...
Page 192
... The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
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... USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). Note that even when no wire mode is selected (USIWM1.. the external clock input (USCK/SCL) are can still be used by the counter. 2570M–AVR–04/11 ATmega325/3250/645/6450 USISIF ...
Page 194
... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked exter- nally, and data input sampled, even when outputs are disabled. The relations between USIWM1:0 and the USI operation is summarized in 2570M–AVR–04/11 ATmega325/3250/645/6450 ...
Page 195
... SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. ATmega325/3250/645/6450 (1) . 195 ...
Page 196
... External, positive edge 1 0 External, negative edge 0 1 External, positive edge 1 1 External, negative edge ATmega325/3250/645/6450 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe ...
Page 197
... BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER (1) OUTPUT 1. See Table 21-1 on page 198. 2. Refer to Figure 1-1 on page 2, Figure 1-2 on page page 72 for Analog Comparator pin placement. ATmega325/3250/645/6450 “Power Reduction Register” on page 37 (2) 3, and “Alternate Functions of Port E” on must be dis- 197 ...
Page 198
... AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see 21.2.2 ACSR – Analog Comparator Control and Status Register Bit 0x30 (0x50) Read/Write Initial Value 2570M–AVR–04/11 ATmega325/3250/645/6450 Analog Comparator Multiplexed Input ADEN MUX2..0 Analog Comparator Negative Input x xxx AIN1 1 ...
Page 199
... Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. 2570M–AVR–04/11 ATmega325/3250/645/6450 199 ...
Page 200
... PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. 2570M–AVR–04/11 ATmega325/3250/645/6450 Table 21-2. ACIS1/ACIS0 Settings ...