ATMEGA325A-AUR Atmel, ATMEGA325A-AUR Datasheet - Page 677

• Manufacturer Part Number: ATMEGA325A-AUR
• Description: IC MCU AVR 32K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8285B–AVR–03/11
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
22 ADC - Analog to Digital Converter ..................................................... 214
23 JTAG Interface and On-chip Debug System ..................................... 232
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 239
25 Boot Loader Support – Read-While-Write Self-Programming ......... 266
22.1Features ..............................................................................................................214
22.2Overview .............................................................................................................214
22.3Operation .............................................................................................................215
22.4Starting a Conversion ..........................................................................................216
22.5Prescaling and Conversion Timing ......................................................................217
22.6Changing Channel or Reference Selection .........................................................219
22.7ADC Noise Canceler ...........................................................................................220
22.8ADC Conversion Result ......................................................................................225
22.9Register Description ............................................................................................227
23.1Features ..............................................................................................................232
23.2Overview .............................................................................................................232
23.3TAP – Test Access Port ......................................................................................233
23.4TAP Controller .....................................................................................................235
23.5Using the Boundary-scan Chain ..........................................................................236
23.6Using the On-chip Debug System .......................................................................236
23.7On-chip Debug Specific JTAG Instructions .........................................................237
23.8Using the JTAG Programming Capabilities .........................................................237
23.9On-chip Debug Related Register in I/O Memory .................................................238
23.10Bibliography .......................................................................................................238
24.1Features ..............................................................................................................239
24.2System Overview ................................................................................................239
24.3Data Registers .....................................................................................................240
24.4Boundary-scan Specific JTAG Instructions .........................................................241
24.5Boundary-scan Chain ..........................................................................................242
24.6Boundary-scan Order ..........................................................................................251
24.7Boundary-scan Description Language Files ........................................................264
24.8Boundary-scan Related Register in I/O Memory .................................................265
25.1Features ..............................................................................................................266
25.2Overview .............................................................................................................266
25.3Application and Boot Loader Flash Sections .......................................................266
25.4Read-While-Write and No Read-While-Write Flash Sections ..............................267
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