ATMEGA325A-AUR Atmel, ATMEGA325A-AUR Datasheet - Page 157

• Manufacturer Part Number: ATMEGA325A-AUR
• Description: IC MCU AVR 32K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.11.4
17.11.5
17.11.6
8285B–AVR–03/11
TIMSK2 – Timer/Counter2 Interrupt Mask Register
TIFR2 – Timer/Counter2 Interrupt Flag Register
ASSR – Asynchronous Status Register
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Coun-
ter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt
Flag Register – TIFR2.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
• Bit 4 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf-
fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
Bit
(0x70)
Read/Write
Initial Value
Bit
0x17 (0x37)
Read/Write
Initial Value
Bit
(0xB6)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
R
5
–
0
EXCLK
R/W
4
0
R
4
–
0
R
4
–
0
AS2
R/W
3
0
R
3
–
0
R
3
–
0
TCN2UB
R
2
0
R
2
–
0
R
2
–
0
OCR2UB
OCIE2A
OCF2A
R
1
0
R/W
R/W
1
0
1
0
TCR2UB
TOIE2
TOV2
R/W
R/W
R
0
0
0
0
0
0
TIMSK2
TIFR2
ASSR
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