ATMEGA325A-AUR Atmel, ATMEGA325A-AUR Datasheet - Page 10

IC MCU AVR 32K FLASH 64TQFP

ATMEGA325A-AUR

Manufacturer Part Number
ATMEGA325A-AUR
Description
IC MCU AVR 32K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA325A-AUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA325A-AUR
Manufacturer:
Atmel
Quantity:
10 000
6. AVR CPU Core
6.1
6.2
10
Introduction
Architectural Overview
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 6-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
Control Lines
Instruction
Instruction
Program
Memory
Block Diagram of the AVR Architecture
Decoder
Register
Flash
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
Comparator
I/O Module1
I/O Module 2
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
Unit
SPI
8285B–AVR–03/11

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