FSAM75SM60A Fairchild Semiconductor, FSAM75SM60A Datasheet - Page 13

• Manufacturer Part Number: FSAM75SM60A
• Description: IC SMART PWR MODULE SPM32-CA
• Manufacturer: Fairchild Semiconductor
• Series: SPM™r
• Type: IGBTr

Specifications of FSAM75SM60A

• Configuration: 3 Phase
• Current: 75A
• Voltage: 600V
• Voltage - Isolation: 2500Vrms
• Package / Case: SPM32CA
• Collector-emitter Saturation Voltage: 2.4 V
• Gate-emitter Leakage Current: 189 W
• Power Dissipation: 189 W
• Mounting Style: SMD/SMT
• Operating Temperature (max): 125C
• Operating Temperature (min): -20C
• Pin Count: 32
• Mounting: Through Hole
• Case Length: 60mm
• Case Height: 7.2mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2006 Fairchild Semiconductor Corporation
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) R
Note:
1) It would be recommended that the bootstrap diode, D
2) The bootstrap resistor (R
3) The ceramic capacitor placed between V
of high-side.
and on the both sides of CPU and SPM for the fault output signal, V
each of SPM pins.
PL
C
PL
/R
PH
CPU
C
These Values depend on PWM Control Algorithm
470uF
PH
/R
PF
15V-Line
C
PF
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
BS
coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to
) should be 3 times greater than R
R
BS
Fig. 12. Recommended CPU I/O Interface Circuit
1nF
CC
-COM should be over 1μF and mounted as close to the pins of the SPM as possible.
100
100
100
47uF
1uF
D
BS
Ω
Ω
Ω
BS
, has soft and fast recovery characteristics.
0.1uF
4.7k
R
C
1nF
PF
E(H)
PF
=
Ω
=
. The recommended value of R
FO
, as close as possible.
0.47nF
C
R
PL
2k
(UL)
PL
=
Ω
=
, IN
5V-Line
IN
COM
IN
COM
Vcc
Vcc
(VL)
One-Leg Diagram of
FSAM75SM60A
, IN
OUT
HO
VB
VS
4.7k
R
C
(WL)
1.2nF
E(H)
PH
PH
, IN
R
=
=
Ω
is 5.6Ω, but it can be increased up to 20Ω for a slower dv/dt
E(H)
(UH)
, IN
(VH)
and IN
COM
IN
V
IN
FO
(UH)
(UL)
(WH)
P
N
,
,
IN
IN
should be placed on the SPM pins
Inverter
Output
(VH)
(VL)
SPM
,
,
IN
IN
(WH)
(WL)
May 4, 2006