ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 61
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 61 of 524
- Download datasheet (5Mb)
9.5 Functional Description
9.5.1 Introduction – IEEE 802.15.4-2006 Frame Format
Figure 9-14. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU)
9.5.1.1 PHY Protocol Layer Data Unit (PPDU)
9.5.1.1.1 Synchronization Header (SHR)
9.5.1.1.2 PHY Header (PHR)
8266A-MCU Wireless-12/09
Figure 9-14 below
defined by IEEE 802.15.4.
medium access control (MAC) layer.
The SHR consists of a four-octet preamble field (all zero), followed by a single byte
start-of-frame delimiter (SFD) which has the predefined value 0xA7. During transmit,
the SHR is automatically generated by the radio transceiver, thus the Frame Buffer
shall contain PHR and PSDU only.
The transmission of the SHR requires 160 µs (10 symbols). As the frame buffer access
is normally faster than the over-air data rate, this allows the application software to
initiate a transmission without having transferred the full frame data already. Instead it is
possible to subsequently write the frame content.
During frame reception, the SHR is used for synchronization purposes. The matching
SFD determines the beginning of the PHR and the following PSDU payload data.
The PHY header is a single octet following the SHR. The least significant 7 bits denote
the frame length of the following PSDU, while the most significant bit of that octet is
reserved, and shall be set to 0 for IEEE 802.15.4 compliant frames.
Register Name
IEEE_ADDR7
….
IEEE_ADDR0
PAN_ID1
PAN_ID0
SHORT_ADDR1
SHORT_ADDR0
XAH_CTRL_0
CSMA_SEED_0
CSMA_SEED_1
CSMA_BE
provides an overview of the physical layer (PHY) frame structure as
Description
Address filter configuration
Short address, PAN-ID and IEEE address
TX_ARET control, retries value control
CSMA-CA seed value
CSMA-CA seed value, RX_AACK control
CSMA-CA back-off exponent control
Figure 9-15 on page 62
ATmega128RFA1
shows the frame structure of the
61
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