ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 137
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 137 of 524
- Download datasheet (5Mb)
10.11 Register Description
10.11.1 SCCNTHH – Symbol Counter Register HH-Byte
8266A-MCU Wireless-12/09
Figure 10-2. Relative Compare Mode
The compare match registers are programmed with symbol intervals relative to the
beacon frame SFD timestamp. For instance the SCCMP1 is programmed to 80,
because the first Granted Time Slot (GTS1) is expected 80 symbols after the beacon
frame. Register SCCMP2 is programmed to 156 to meet GTS3 156 symbols after the
beacon frame. SCCMP3 is programmed to 312. This is the time interval where the
beacon of the next superframe is expected. Because it requires some time to activate
the transceiver and there is also some timing drift possible, the compare interrupt must
be programmed to wake up some symbols in advance to make sure the next beacon is
not missed.
If the controller receives a compare match wake up event it is activating the transceiver.
After the frame operations are finished, the system can go back to sleep until the next
compare match event occurs.
This register contains the most significant byte of the 32 bit Symbol Counter.
• Bit 7:0 – SCCNTHH7:0 - Symbol Counter Register HH-Byte
Bit
NA ($E4)
Read/Write
Initial Value
RW
7
0
RW
6
0
RW
5
0
SCCNTHH7:0
RW
4
0
RW
3
0
RW
2
0
ATmega128RFA1
RW
1
0
RW
0
0
SCCNTHH
137
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