ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 469
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 469 of 524
- Download datasheet (5Mb)
31.7 Parallel Programming
31.7.1 Enter Programming Mode
8266A-MCU Wireless-12/09
Table 31-11. Pin Values Used to Enter Programming Mode
Table 31-12. XA1 and XA0 Encoding
Table 31-13. Command Byte Bit Encoding
Pulses of CLKI and in the following command sequences are assumed to be at least
250 ns wide unless otherwise noted.
The following algorithm puts the device in parallel programming mode:
1. Apply 3.3V between DEVDD and DVSS.
2. Set RSTN to 0 and TST to 0.
3. Set the Prog_enable pins listed in
4. Set TST to 1. TST can be set high any time before but not after the rising edge of
5. Set RSTN to 1. Any activity on Prog_enable pins within 100 ns after RSTN is set to 1
6. Wait at least 50 µs before sending a command.
100ns.
RSTN (t
will cause the device to fail entering programming mode.
XA1
0
0
1
1
Command Byte
1000 0000
0100 0000
0010 0000
0001 0000
0001 0001
0000 1000
0000 0100
0000 0010
0000 0011
PAGEL
TSTRNH
XA1
XA0
BS1
Pin
).
XA0
0
1
0
1
Action when CLKI is Pulsed
Load Flash or EEPROM Address (High or low address byte
determined by BS2 and BS1).
Load Data (High or Low data byte for Flash determined by
BS1).
Load Command.
No Action, Idle.
Command Executed
Chip Erase
Write Fuse bits
Write Lock bits
Write Flash
Write EEPROM
Read Signature bytes and Calibration byte
Read Fuse and Lock bits
Read Flash
Read EEPROM
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
Table 31-11 above
Symbol
ATmega128RFA1
to “0000” and wait at least
Value
0
0
0
0
469
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