ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 444
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 444 of 524
- Download datasheet (5Mb)
29.4.3 SAMPLE_PRELOAD; 0x2
29.4.4 AVR_RESET; 0xC
29.4.5 BYPASS; 0xF
29.5 Boundary-scan Chain
29.5.1 Scanning the Digital Port Pins
444
ATmega128RFA1
The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
the input/output pins without affecting the system operation. However, the output
latches are not connected to the pins. The Boundary-scan Chain is selected as Data
Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches.
The AVR specific public JTAG instruction for forcing the AVR device into the Reset
mode or releasing the JTAG reset source. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic “one” in the Reset Chain. The output from this
chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connection.
Figure 29-3 on page 445
pull-up function is disabled during Boundary-scan when the JTAG IC contains EXTEST
or SAMPLE_PRELOAD. The cell consists of a bi-directional pin cell that combines the
three signals Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into
only a two-stage Shift Register. The port and pin indexes are not used in the following
description.
The Boundary-scan logic is not included in the figures in the datasheet.
page 446
186. The Boundary-scan details from
in
Figure 29-4 on page
Chain.
However, the output latches are not connected to the pins.
shows a simple digital port pin as described in the section
446.
shows the Boundary-scan Cell for a bi-directional port pin. The
Figure 29-3 on page 445
replaces the dashed box
8266A-MCU Wireless-12/09
"I/O-Ports" on page
Figure 29-4 on
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