ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 504

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

34.6 SPI Timing Characteristics
504
Symbol
V
V
V
t
t
t
r
of
SP
IH
hys
OL
Parameter
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both SDA and SCL
Output Fall Time from V
Spikes suppressed by the input filter
ATmega128RFA1
IHmin
Note:
Figure 34-2
SCL
SDA
See Figure 34-3and Figure 34-4 for details.
Table 34-9. SPI Timing Parameters
Description
SCK period
SCK high/low
Rise/fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS
SCK period
SCK high/low
Rise/fall time
Setup
Hold
SCK to out
SCK to SS
SS
SS
__
__
__
low to out
high to tri-state
low to SCK
to V
t
SU;STA
__
ILmax
1. In SPI Programming mode the minimum SCK high/low period is 2 t
high
MHz and 3 t
(1)
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
CLCL
t
HD;STA
t
of
t
LOW
for f
Condition
3mA sink current
4 t
2 t
TBD
TBD
TBD
CK
Min
t
CK
CK
CK
> 12 MHz.
t
HIGH
t
See
HD;DAT
"SPCR – SPI Control Register" on
t
LOW
50% duty cycle
page
0.5 t
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
Typ
SU;DAT
0.7V
336.
SCK
Min.
0
DEVDD
V
DEVDD
Max.
8266A-MCU Wireless-12/09
300
250
0.4
50
t
SU;STO
+0.5
CLCL
TBD
Max
t
r
for f
Units
CK
Units
ns
ns
ns
V
V
V
ns
< 12
t
BUF