ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 478
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 478 of 524
- Download datasheet (5Mb)
31.8.2 Serial Programming Algorithm
478
ATmega128RFA1
Figure 31-13. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed
programming operation (in the Serial mode ONLY) and there is no need to first execute
the Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega128RFA1, data is clocked on the rising edge of
SCK.
When reading data from the ATmega128RFA1, data is clocked on the falling edge of
SCK. See
To program and verify the ATmega128RFA1 in the serial programming mode, the
following sequence is recommended (See four byte instruction formats in
on
1. Power-up sequence: Apply power between DEVDD and DVSS while RSTN and
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of
page 479):
SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is
held low during power-up. In this case, RSTN must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
Enable serial instruction to pin PDI.
synchronization. When in sync. the second byte (0x53), will echo back when issuing
the third byte of the Programming Enable instruction. Whether the echo is correct or
1. If the device is clocked by the internal Oscillator, it is not required to connect a
2. V
Figure 31-15 on
clock source to the CLKI pin.
supply voltage limits.
DEVDD
-0.3V < V
EVDD
page 481 for timing details.
ck
< V
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
DEVDD
+0.3V, both V
(1)(2)
EVDD
and V
DEVDD
ck
8266A-MCU Wireless-12/09
ck
must stay in valid
>= 12 MHz;
>= 12 MHz;
Table 31-17
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