ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 412
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 412 of 524
- Download datasheet (5Mb)
cause instable operation of the internal reference voltage buffer and will not improve
noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX and
ADCSRB. Any of the ADC input pins, as well as AVSS and a fixed bandgap voltage
reference can be selected as single ended inputs to the ADC. A choice of ADC input
pins can be selected as positive and negative inputs to the differential amplifier.
Furthermore the temperature sensor and the DRT voltages of SRAM2 can also be
processed with the
ADC.
If differential channels are selected, the amplified voltage difference between the
selected input channel pair then becomes the input of the ADC. The respective pin
voltages for a differential measurement can be in the range from 0V to EVDD. In this
way it is possible to handle differential input voltages with a common mode value higher
than AVDD e.g. process a 50mV differential signal with a 2.5V common mode voltage.
If single ended channels are used, the gain amplifier is bypassed altogether. Any ADC
input voltage (single-ended or amplified-differential) exceeding AVDD will be internally
clamped to AVDD to avoid damaging the ADC circuitry. Note that the pin input current
will not increase if the clamp circuit is active.
The ADC is enabled by setting ADEN bit in ADCSRA. Voltage reference and input
channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared. It is required to disable the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the
content of the Data Registers belongs to the same conversion. Once ADCL is read,
ADC access to Data Registers is blocked. This means that if ADCL has been read, and
a conversion completes before ADCH is read, neither register is updated and the result
from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL
Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the Data Registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
27.3 ADC Start-Up
After the ADC is enabled by setting ADEN, it will go through a start-up phase. The
analog supply voltage AVDD is turned on. It takes time t
(see
"Power Management
AVREG
Electrical Characteristics" on page
503) µs for AVDD to stabilize. A stable AVDD
voltage is indicated by the AVDDOK bit in ADCSRB. After this the ADC and, for
differential input channels also the gain amplifier, is powered up. The duration of this
phase depends on the ADC clock period and the configuration of the Start-Up and
Track-And–Hold Time bits, ADSUT4:0 and ADTHT1:0 in ADCSRC. For details about
the start-up timing refer to section
"Pre-scaling and Conversion Timing" on
page 413.
During the ADC start-up phase a conversion start can already be requested by writing a
logical one to the ADC Start Conversion bit, ADSC in ADCSRA. In this case a
conversion is started directly after the start-up phase. During the start-up phase it is still
possible to change the analog input channel until the AVDDOK bit changes to logic one
or, if the AVDDOK bit is one, until the ADSC bit is set.
ATmega128RFA1
412
8266A-MCU Wireless-12/09
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