ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 440
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 440 of 524
- Download datasheet (5Mb)
28.9 Bibliography
28.10 On-chip Debug Related Register in I/O Memory
28.10.1 OCDR – On-Chip Debug Register
440
ATmega128RFA1
The JTAG programming capability supports:
• Flash programming and verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programming and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or
LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a
chip erase. This is a security feature that ensures no back-door exists for reading out
the content of a secured device.
The details on programming through the JTAG interface and programming specific
JTAG instructions are given in the section
page
For more information about general Boundary-scan, the following literature can be
consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-
The OCDR Register provides a communication channel from the running program in
the microcontroller to the debugger. The CPU can transfer a byte to the debugger by
writing to this location. At the same time, an internal flag; I/O Debug Register Dirty
IDRD is set to indicate to the debugger that the register has been written. When the
CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the
MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the
information. In some AVR devices, this register is shared with a standard I/O location.
In this case, the OCDR Register can only be accessed if the OCDEN Fuse is
programmed, and the debugger enables access to the OCDR Register. In all other
cases, the standard I/O location is accessed.
• Bit 7:0 – OCDR7:0 - On-Chip Debug Register Data
Table 28-16 OCDR Register Bits
Bit
$31 ($51)
Read/Write
Initial Value
Register Bits
OCDR7:0
Architecture, IEEE, 1993.
Wesley, 1992.
481.
RW
7
0
RW
6
0
RW
5
0
Value
RW
4
0
0
OCDR7:0
RW
3
0
"Programming via the JTAG Interface" on
Description
Refer to the debugger documentation for
further information on how to use this
register.
RW
2
0
RW
1
0
RW
0
0
8266A-MCU Wireless-12/09
OCDR
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