ATA3745P3-TGQY Atmel, ATA3745P3-TGQY Datasheet - Page 15

• Manufacturer Part Number: ATA3745P3-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3745P3-TGQY

• Frequency: 310MHz ~ 440MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA3745P3-TGQYTR

5.3.2
5.4
5.4.1
Figure 5-8.
4901B–RKE–11/07
Receiving Mode
Clock bit check
Duration of the Bit Check
Digital Signal Processing
counter
Dem_out
Synchronization of the Demodulator Output
DATA
If no transmitter signal is present during the bit check, the output of the demodulator delivers
random signals. The bit check is a statistical process and T
Therefore, an average value for T
page
range causes a lower value for T
In the presence of a valid transmitter signal, T
nal, f
in a longer period for T
If the bit check has been successful for all bits specified by N
receiving mode. As seen in
DATA in that case. A connected microcontroller can be woken up by the negative edge at pin
DATA. The receiver stays in that condition until it is switched back to polling mode explicitly.
The data from the demodulator (Dem_out) is digitally processed in different ways and as a
result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range).
clock cycle T
only after T
always an integral multiple of T
The minimum time period between two edges of the data signal is limited to t
This implies an efficient suppression of spikes at the DATA output. At the same time, it limits
the maximum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. T
val t
the following level is frozen for the time period T
limits, T
The maximum time period for DATA to be low is limited to T
finite response time during programming or switching off the receiver via pin DATA.
T
stream.
receiver has switched to receiving mode.
DATA_L_max
T
XClk
ee
Sig
23. T
as illustrated in
DATA_min
and the count of the checked bits, N
Figure 5-10 on page 16
Bitcheck
XClk
is thereby longer than the maximum time period indicated by the transmitter data
XClk
= tmin2 is the relevant stable time period.
elapsed. The edge-to-edge time period t
. This clock is also used for the bit check counter. Data can change its state
DATA_min
depends on the selected baud rate range and on T
Figure 5-9 on page
Bitcheck
Figure 5-8
is to some extent affected by the preceding edge-to-edge time inter-
Figure 5-4 on page
requiring a higher value for the transmitter preburst T
XClk
t
Bitcheck
ee
Bitcheck
.
gives an example where Dem_out remains low after the
illustrates how Dem_out is synchronized by the extended
resulting in lower current consumption in polling mode.
is given in the section
16. If t
Bitcheck
Bitcheck
13, the internal data signal is switched to pin
ee
DATA_min
. A higher value for N
is in between the specified bit check limits,
is dependant on the frequency of that sig-
= tmin1; if t
ee
DATA_L_max
of the Data signal, as a result, is
Bitcheck
Bitcheck
“Electrical Characteristics” on
ee
, the receiver switches to
. This function ensures a
varies for each check.
is outside the bit check
Clk
Bitcheck
. A higher baud rate
ATA3745
thereby results
ee
Preburst
T
DATA_min
.
15
.