ATA3745P3-TGQY Atmel, ATA3745P3-TGQY Datasheet - Page 13

• Manufacturer Part Number: ATA3745P3-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3745P3-TGQY

• Frequency: 310MHz ~ 440MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA3745P3-TGQYTR

5.3
5.3.1
4901B–RKE–11/07
Bit Check Mode
Configuring the Bit Check
In bit check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a
programmable time window. The maximum count of this edge-to-edge test, before the
receiver switches to receiving mode, is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The max-
imum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N
set to a higher value, the receiver is less likely to switch to the receiving mode due to noise. In
the presence of a valid transmitter signal, the bit check takes less time if N
lower value. In polling mode, the bit check time is not dependent on N
page 12
ferred to pin DATA.
Figure 5-4
If the edge-to-edge time t
check limit T
T
Figure 5-4.
For best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard.
A good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t
ous edge-to-edge time periods, the bit check limits must be programmed according to the
required span.
The bit check limits are determined by means of the formulas below:
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the
required T
T
“Receiving Mode” on page
maximum value of the upper limit is Lim_max = 63.
Lim_max
Lim_min
Lim_max
XClk
. The minimum edge-to-edge time t
, the bit check will be terminated and the receiver switches to sleep mode.
= Lim_min
= (Lim_max – 1)
shows an example where 3 bits are tested successfully and the data signal is trans-
Lim_min
shows that the time window for the bit check is defined by two separate time limits.
Lim_max
Valid Time Window for Bit Check
, T
Lim_max
, the check will be continued. If t
Dem_out
T
XClk
and T
ee
15. Due to this, the lower limit should be set to Lim_min
T
is in between the lower bit check limit T
XClk
XClk
. The time resolution when defining T
T
T
Lim_max
Lim_min
T
ee
ee
(t
DATA_L_min
1/f
ee
Sig
. Using preburst patterns that contain vari-
ee
is smaller than T
, t
DATA_H_min
Lim_min
) is defined in Section
Bitcheck
Lim_min
Lim_min
Lim_min
and the upper bit
ATA3745
Bitcheck
.
and T
or t
Figure 5-3 on
and T
Bitcheck
ee
is set to a
Lim_max
exceeds
Bitcheck
10. The
Lim_max
in the
13
is
is
.