AD6655BCPZ-105 Analog Devices Inc, AD6655BCPZ-105 Datasheet - Page 5

• Manufacturer Part Number: AD6655BCPZ-105
• Description: IC IF RCVR 14BIT 105MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-105

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 575mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Data Rate Max: 105Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SPECIFICATIONS
ADC DC SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
MATCHING CHARACTERISTIC
TEMPERATURE DRIFT
INTERNAL VOLTAGE REFERENCE
INPUT-REFERRED NOISE
ANALOG INPUT
VREF INPUT RESISTANCE
POWER SUPPLIES
POWER CONSUMPTION
1
2
3
4
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See
Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the f
5 pF loading on each output bit.
The maximum limit applies to the combination of I
Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).
No Missing Codes
Offset Error
Gain Error
Offset Error
Gain Error
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
VREF = 1.0 V
Input Span, VREF = 1.0 V
Input Capacitance
Supply Voltage
Supply Current
DC Input
Sine Wave Input
Sine Wave Input
Standby Power
Power-Down Power
Offset Error
Gain Error
DRVDD (LVDS Mode)
AVDD, DVDD
DRVDD (CMOS Mode)
I
I
I
I
I
AVDD
DVDD
DRVDD
DRVDD
DRVDD
2, 3
2, 3
2
2
2
(3.3 V CMOS)
(1.8 V CMOS)
(1.8 V LVDS)
2
2
4
(DRVDD = 1.8 V)
(DRVDD = 3.3 V)
1
Temperature
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AVDD
and I
DVDD
currents.
Min
14
−3.6
1.7
1.7
1.7
Rev. A | Page 5 of 8
AD6655BCPZ-80
Typ
±0.2
−1.8
±0.2
±0.2
±15
±95
±5
7
0.85
2
8
6
1.8
3.3
1.8
235
175
18
8
55
470
755
800
52
2.5
Guaranteed
Max
±0.6
−0.1
±0.6
±0.75
±18
1.9
3.6
1.9
420
490
8
Figure 11
Min
14
−4.3
1.7
1.7
1.7
for the equivalent analog input structure.
AD6655BCPZ-105
S
/8 output mix enabled with approximately
Typ
±0.2
−2.2
±0.2
±0.2
±15
±95
±5
7
0.85
2
8
6
1.8
3.3
1.8
315
225
21
11
56
620
995
1040
68
2.5
Guaranteed
Max
±0.6
−0.5
±0.6
±0.75
±18
1.9
3.6
1.9
575
650
8
AD6655
Unit
Bits
% FSR
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW