AD6655BCPZ-105 Analog Devices Inc, AD6655BCPZ-105 Datasheet - Page 29

• Manufacturer Part Number: AD6655BCPZ-105
• Description: IC IF RCVR 14BIT 105MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-105

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 575mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Data Rate Max: 105Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

THEORY OF OPERATION
The AD6655 has two analog input channels, two decimating
channels, and two digital output channels. The intermediate
frequency (IF) input signal passes through several stages before
appearing at the output port(s) as a filtered, decimated digital
signal.
The dual ADC design can be used for diversity reception of
signals, where the ADCs operate identically on the same carrier
but from two separate antennae. The ADCs can also be operated
with independent analog inputs. The user can sample any f
frequency segment from dc to 150 MHz using appropriate low-
pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 450 MHz analog input is
permitted but occurs at the expense of increased ADC noise and
distortion.
In nondiversity applications, the AD6655 can be used as a base-
band receiver, where one ADC is used for I input data, and the
other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices. The
NCO phase can be set to produce a known offset relative to
another channel or device.
Programming and control of the AD6655 are accomplished
using a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE
AD6655 architecture consists of a front-end sample-and-hold
amplifier (SHA) followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined archi-
tecture permits the first stage to operate on a new input sample
and the remaining stages to operate on the preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
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ANALOG INPUT CONSIDERATIONS
The analog input to the AD6655 is a differential switched-
capacitor SHA that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 46). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the inputs
to provide dynamic charging currents. This passive network creates
a low-pass filter at the ADC input; therefore, the precise values
are dependent on the application.
In IF undersampling applications, any shunt capacitors should be
reduced. In combination with the driving source impedance,
the shunt capacitors limit the input bandwidth. Refer to Appli-
cation Note AN-742, Frequency Domain Response of Switched-
Capacitor ADCs; Application Note AN-827, A Resonant Approach
to Interfacing Amplifiers to Switched-Capacitor ADCs; and the
Analog Dialogue article, “Transformer-Coupled Front-End for
Wideband A/D Converters, ” for more information on this subject
(see www.analog.com). In general, the precise values are dependent
on the application.
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the
ADC core. The output common mode of the reference buffer is
set to V
Input Common Mode
The analog inputs of the AD6655 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that V
recommended for optimum performance, but the device functions
over a wider range with reasonable performance (see Figure 45).
VIN+
VIN–
CMREF
C
C
PIN, PAR
PIN, PAR
(approximately 1.6 V).
Figure 46. Switched-Capacitor SHA Input
S
S
H
C
C
S
S
CM
= 0.55 × AVDD is
C
C
S
S
H
H
AD6655