AD6655BCPZ-105 Analog Devices Inc, AD6655BCPZ-105 Datasheet - Page 15

• Manufacturer Part Number: AD6655BCPZ-105
• Description: IC IF RCVR 14BIT 105MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-105

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 575mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Data Rate Max: 105Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Table 9.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
SPORT TIMING REQUIREMENTS
Timing Diagrams
Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSSCLK
SSLKSDO
SSCLKSDFS
DCOA/DCOB
CMOS DATA
DECIMATED
DECIMATED
DECIMATED
DCOA/DCOB
CMOS DATA
DECIMATED
DECIMATED
DECIMATED
FD DATA
FD DATA
CLK+
CLK+
Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CHANNEL A/B
FD BITS
t
PD
t
PD
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
CHANNEL A/B
FD BITS
t
S
t
S
CHANNEL A/B
CHANNEL A/B
DATA BITS
CHANNEL A/B
FD BITS
DATA BITS
CHANNEL A/B
FD BITS
t
H
Rev. A | Page 15 of 88
t
H
CHANNEL A/B
FD BITS
CHANNEL A/B
CHANNEL A/B
t
CHANNEL A/B
DCO
DATA BITS
DATA BITS
FD BITS
t
DCO
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
CHANNEL A/B
Min
2
2
40
2
2
10
10
10
3.2
−0.4
−0.4
10
DATA BITS
FD BITS
CHANNEL A/B
DATA BITS
Typ
0.24
0.4
4.5
0
0
Max
6.2
+0.4
+0.4
AD6655
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns