AD6655BCPZ-105 Analog Devices Inc, AD6655BCPZ-105 Datasheet
AD6655BCPZ-105
Specifications of AD6655BCPZ-105
Related parts for AD6655BCPZ-105
AD6655BCPZ-105 Summary of contents
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FEATURES SNR = 74.5 dBc (75.5 dBFS 32.7 MHz MHz @ 150 MSPS SFDR = 80 dBc to 70 MHz @ 150 MSPS 1.8 V analog supply operation 1 3.3 V CMOS output ...
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... General Description ......................................................................... 4 Specifications ..................................................................................... 5 ADC DC Specifications—AD6655BCPZ-80/ AD6655BCPZ-105 ......................................................................... 5 ADC DC Specifications—AD6655BCPZ-125/ AD6655BCPZ-150 ......................................................................... 6 ADC AC Specifications—AD6655BCPZ-80/ AD6655BCPZ-105 ......................................................................... 7 ADC AC Specifications—AD6655BCPZ-125/ AD6655BCPZ-150 ......................................................................... 8 Digital Specifications—AD6655BCPZ-80/AD6655BCPZ-105 .. 9 Digital Specifications—AD6655BCPZ-125/ AD6655BCPZ-150 ....................................................................... 11 Switching Specifications—AD6655BCPZ-80/ AD6655BCPZ-105 ....................................................................... 13 Switching Specifications—AD6655BCPZ-125/ AD6655BCPZ-150 ....................................................................... 14 Timing Specifications ................................................................ 15 Absolute Maximum Ratings .......................................................... 18 Thermal Characteristics ............................................................ 18 ESD Caution ...
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Output Signals ............................................................................. 61 Default Operation and Jumper Selection Settings .................. 62 Alternative Clock Configurations ............................................. 62 Alternative Analog Input Drive Configuration ...................... 63 Schematics .................................................................................... 64 REVISION HISTORY 9/09—Rev Rev. A Added Exposed Pad Notation to Figure ...
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AD6655 GENERAL DESCRIPTION The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small ...
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... SPECIFICATIONS ADC DC SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION Full ACCURACY No Missing Codes Full Offset Error Full Gain Error Full ...
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... AD6655 ADC DC SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error ...
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... ADC AC SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 3. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR 2.4 MHz MHz ...
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... AD6655 ADC AC SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 4. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR 2.4 MHz ...
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... DIGITAL SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = DCS enabled, unless otherwise noted. Table 5. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage ...
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... Full 1.75 Full 0.2 Full 0.05 Full 250 350 450 Full 1.15 1.25 1.35 Full 150 200 280 Full 1.15 1.25 1.35 Full Rev Page AD6655BCPZ-105 Min Typ Max Unit 1.22 3 0.6 V −90 −134 μA −10 +10 μA 26 kΩ 3. ...
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... DIGITAL SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage ...
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... Full 0.2 Full 0.05 Full 250 350 450 Full 1.15 1.25 1.35 Full 150 200 280 Full 1.15 1.25 1.35 Rev Page AD6655BCPZ-150 Min Typ Max 1.22 3.6 0 0.6 −90 −134 −10 + 3.29 3.25 0.2 0.05 1.79 1.75 0.2 0.05 ...
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... SWITCHING SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105 Table 7. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High (t ) CLKH Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode DCS Disabled Divide-by-2 Mode, DCS Enabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode— ...
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... AD6655 SWITCHING SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150 Table 8. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High (t ) CLKH Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode, DCS Enabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode— ...
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TIMING SPECIFICATIONS Table 9. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time SSYNC t SYNC to the rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data ...
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AD6655 CLK DECIMATED CHANNEL A: CHANNEL B: INTERLEAVED DATA CMOS DATA DECIMATED CHANNEL A: CHANNEL B: INTERLEAVED FD BITS FD DATA DECIMATED DCO Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing CLK ...
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CLK+ CLK– t CSSCLK SMI SCLK t SSCLKSDFS SMI SDFS SMI SDO t SSCLKSDFS DATA Figure 8. Signal Monitor SPORT Output Timing Rev Page AD6655 DATA ...
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AD6655 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND VIN+A/VIN+B, VIN-A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRVDD D10B D11B D12B D13B (MSB) DCOB DCOA D0A (LSB) NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED ...
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AD6655 Pin No. Mnemonic Type Digital Input 52 SYNC Input Digital Outputs 12 D0A (LSB) Output 13 D1A Output 14 D2A Output 15 D3A Output 16 D4A Output 17 D5A Output 18 D6A Output 19 D7A Output 22 D8A Output ...
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DRVDD D1– D1+ D2– D2+ D3– D3+ D4– D4+ DCO– DCO+ D5– D5+ D6– D6+ D7– NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE ...
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AD6655 Pin No. Mnemonic Type Digital Input 52 SYNC Input Digital Outputs 63 D0+ (LSB) Output 62 D0− (LSB) Output 3 D1+ Output 2 D1− Output 5 D2+ Output 4 D2− Output 7 D3+ Output 6 D3− Output 9 D4+ ...
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EQUIVALENT CIRCUITS VIN Figure 11. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 12. Equivalent Clock lnput Circuit DRVDD DRGND Figure 13. Equivalent Digital Output Circuit DRVDD DRVDD 26kΩ 1kΩ SDIO/DCS Figure 14. Equivalent SDIO/DCS Circuit or SMI ...
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AD6655 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference p-p differential input, VIN = −1.0 dBFS, 64k sample ...
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SNR = 67.4dBc (65.4dBFS) –20 SFDR = 74.1dBc f = 429MHz NCO –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 25. AD6655-150 Single-Tone FFT with ...
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AD6655 120 100 SFDR (dBFS) SNR (dBFS SFDR (dBc) 20 SNR (dBc) 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 31. AD6655-150 Single-Tone SNR/SFDR vs. Input Amplitude ( 2.4 MHz ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 IMD3 (dBFS) SFDR (dBFS) –100 –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 37. AD6655-150 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 169.12 MHz 172.12 MHz, ...
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AD6655 – – – OUTPUT CODE Figure 43. AD6655 Grounded Input Histogram 90 85 SFDR DCS ON SFDR DCS OFF 80 SNR DCS ON 75 SNR ...
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THEORY OF OPERATION The AD6655 has two analog input channels, two decimating channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port( filtered, decimated digital signal. ...
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AD6655 An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum perform- ance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 ...
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Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common- mode swing. If the source impedances on each input are matched, there should ...
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AD6655 If the internal reference of the AD6655 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 54 depicts how the internal reference voltage is affected ...
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CLOCK INPUT AD951x PECL DRIVER 0.1µF CLOCK INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 59. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as ...
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AD6655 75 MEASURED INPUT FREQUENCY (MHz) Figure 63. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the ...
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TOTAL POWER IAVDD 0.50 IDVDD 0.25 IDRVDD SAMPLE RATE (MSPS) Figure 67. AD6655-80 Power and Current vs. Sample Rate By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), ...
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AD6655 Table 17. Output Data Format Input (V) Condition (V) VIN+ – VIN– < –VREF – 0.5 LSB VIN+ – VIN– = –VREF VIN+ – VIN– VIN+ – VIN– = +VREF – 1.0 LSB VIN+ – VIN– > ...
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DIGITAL DOWNCONVERTER The AD6655 includes a digital processing section that provides filtering and reduces the output data rate. This digital processing section includes a numerically controlled oscillator (NCO), a half-band decimating filter, an FIR filter, and a second coarse NCO ...
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AD6655 NUMERICALLY CONTROLLED OSCILLATOR (NCO) FREQUENCY TRANSLATION This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The two channels of the AD6655 share a single NCO. The NCO is optional and can be ...
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DECIMATING HALF-BAND FILTER AND FIR FILTER The goal of the AD6655 half-band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. This filter ...
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AD6655 Table 20. FIR Filter Coefficients Coefficient Normalized Number Coefficient C0, C65 0.0001826 C1, C64 0.0006824 C2, C63 0.0009298 C3, C62 0.0000458 C4, C61 −0.0012689 C5, C60 −0.0008345 C6, C59 0.0011806 C7, C58 0.0011387 C8, C57 −0.0018439 C9, C56 −0.0024557 ...
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ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor- mation on the state of the analog ...
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AD6655 When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins are available. In these modes, the fast detect output pins have a latency of six clock cycles, ...
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Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold ...
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AD6655 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a ...
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In addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples. Figure 77 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP POWER MONITOR DOWN IS COUNT = 1? ...
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AD6655 DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction control register located at ...
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CHANNEL/CHIP SYNCHRONIZATION The AD6655 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, half-band filters, and ...
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AD6655 SERIAL PORT INTERFACE (SPI) The AD6655 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOS- compatible control pins. When the device ...
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AD6655 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 29 are not currently supported for this device. Table 29. Memory Map Registers Addr. Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...
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AD6655 Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0D Test Mode Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output strength type 3 CMOS V CMOS or 1 ...
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Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x104 Fast Detect Open Open Control (Local) 0x105 Coarse Upper Open Open Threshold (Local) 0x106 Fine Upper Threshold Register 0 (Local) 0x107 Fine Upper Open Open Threshold Register 1 (Local) 0x108 ...
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AD6655 Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x112 Signal Complex Open Monitor power Control calculation (Global) mode enable 0x113 Signal Monitor Period Register 0 (Global) 0x114 Signal Monitor Period Register 1 (Global) 0x115 Signal Monitor Period Register ...
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Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x121 NCO Frequency 3 0x122 NCO Phase Offset 0 0x123 NCO Phase Offset 1 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0xFF, see ...
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AD6655 Digital Filter Control (Register 0x103) Bits[7:4]—Reserved Bit 3—Half-Band Decimation Phase When set high, Bit 3 uses the alternate phase of the decimating half-band filter. Bit 2—Spectral Reversal Bit 2 enables the spectral reversal feature of the half-band filter. Bit ...
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Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x110, Bits[7:6]—Reserved Register 0x110, Bits[5:0]—Channel B DC Value Bits[13:8] Register 0x10F, Bits[7:0]—Channel B DC Value Bits [7:0] These read-only registers hold the latest dc offset value computed by ...
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AD6655 Bit 0—NCO32 Enable When Bit 0 is set, this bit enables the 32-bit NCO operating at the frequency programmed into the NCO frequency register. When Bit 0 is cleared, the NCO is bypassed and shuts down for power savings. ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system-level design and layout of the AD6655 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground ...
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AD6655 To avoid this additional DRVDD current, the AD6655 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed into LVDS mode via the SPI port, the OEB pin can be taken low ...
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EVALUATION BOARD The AD6655 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura- tions. The converter can be driven differentially through a double balun configuration (default) or optionally through the ...
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AD6655 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD6655 evaluation board. POWER Connect the switching power supply that is provided in the evaluation kit between ...
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ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 ...
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AD6655 SCHEMATICS OHM 10K R41 OHM 100 7 R12 4.12K R126 DNP R36 OHM 24.9 OHM 24.9 R29 R35 F Figure 85. Evaluation Board Schematic, Channel A Analog Inputs Rev Page 06709-200 OHM 57.6 R5 ...
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M OH 10K R53 AMPVDD M OH 100 R129 4.12K R128 P DN R68 24.9 R134 R135 F Figure 86. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06709-201 ...
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AD6655 10KOHM 10KOHM R85 24.9OHM R83 F R82 OHM 0 R8 57.6OHM R30 2 Figure 87. Evaluation Board Schematic, DUT Clock Input Rev Page 06709-202 TP2 1 2 DNP R34 57.6OHM R7 2 ...
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OHM 100 R75 OHM 100 VS_OUT67_ 50 VS_OUT67_ 2 51 VS_OUT01_DI OUT1 53 1 OUT 54 VS_OUT01_DR OUT0 56 0 OUT 57 F VS_RE 4.12K 58 RSET_CLOC K R12 ...
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AD6655 A C Figure 89. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input RES0402 M OH 10K R105 RES0402 M OH 10K R103 RES0402 M OH 10K R102 RES0402 M OH 10K R100 RES0402 M OH 10K R107 ...
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DVDD RPAK8 22ohm 29 A FD0 FD1 FD2 FD3 4 13 PWR_SDO PWR_SCL ...
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AD6655 10KOHM R118 2 RES040 VAL R130 2 RES040 10KOHM R140 Figure 91. Evaluation Board Schematic, Digital Output Interface Rev Page 06709-206 100OHM R77 ...
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Figure 92. Evaluation Board Schematic, SPI Circuitry Rev Page AD6655 06709-207 2 RES040 10KOHM R65 ...
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AD6655 GND 4 1 RES0603 M OH 261 A C R16 CR7 2 1 S2A_REC T M KOH 76 147K R13 R14 SJ35 Figure 93. Evaluation Board Schematic, Power Supply Rev Page 06709-208 ...
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GND 4 1 SJ37 SJ36 GND GND Figure 94. Evaluation Board Schematic, Power Supply (Continued) Rev Page 140KOH M 78.7KOH R25 R15 AD6655 06709-209 ...
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AD6655 EVALUATION BOARD LAYOUTS Figure 95. Evaluation Board Layout, Primary Side Rev Page ...
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Figure 96. Evaluation Board Layout, Ground Plane Rev Page AD6655 ...
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AD6655 Figure 97. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 98. Evaluation Board Layout, Power Plane Rev Page AD6655 ...
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AD6655 Figure 99. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD6655 ...
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AD6655 Figure 101. Evaluation Board Layout, Silkscreen, Primary Side Rev Page ...
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Figure 102. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page AD6655 ...
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AD6655 BILL OF MATERIALS Table 30. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD6655CE_REVB PCB C3, C6, C7, 0.1 μ ceramic C13, C14, C17, C18, capacitor, SMT 0402 ...
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... SOT223-HS Analog Devices SOT223-HS Analog Devices OSC-CTS-CB3 Valpey Fisher LFCSP16-3X3-PAD Analog Devices Rev Page AD6655 Mfg. Part Number NRC06F2610TRF NRC06F1003TRF NRC04F1002TRF NRC06F1001TRF NRC04J330TRF 742C163220JPTR 742C083220JPTR NCR04F2000TRF 142-0701-201 NRC10ZOTRF MABA-007159-000000 AD6655BCPZ AD9516-4BCPZ NC7WZ04P6X_NL NC7WZ07P6X_NL NC7WZ16P6X_NL 74VCX16244MTDX_NL ADP3334ACPZ ADP3339AKCZ-1.8 ADP3339AKCZ-5.0 ADP3339AKCZ-3.3 VFAC3-BHL AD8352ACPZ ...
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AD6655 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 ...
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... AD6655ABCPZRL7-125 −40°C to +85°C 1 AD6655BCPZ-150 −40°C to +85°C 1 AD6655BCPZ-125 −40°C to +85°C 1 AD6655BCPZ-105 −40°C to +85°C 1 AD6655BCPZ-80 −40°C to +85°C 1 AD6655-125EBZ 1 AD6655-150EBZ RoHS Compliant Part. Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...
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AD6655 NOTES Rev Page ...
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NOTES Rev Page AD6655 ...
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AD6655 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06709-0-9/09(A) Rev Page ...