MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 745

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Freescale Semiconductor
Table 8-5/Page 8-6 CWCR[CWRI] bit description, change “...is programmed in the interrupt control register 7 (ICR7)...” to “...is
Table 9-4/Page 9-7 In the table for MFD bit definition, footnote (1) equation should read:
10.3.6/Page 10-11
10.3.7/Page 10-16
Section 16.5/Page
Table 10-14/Page
Figure 10-6/Page
Figure 15-1/Page
Table 12-7/Page
Table 10-2/Page
Table 15-1/Page
Table 15-5/Page
Chapter 8
Location
Section
Section
10-15
16-11
10-9
12-7
10-4
15-1
15-3
15-7
Remove any references to the core watchdog timer being able to reset the device. It is only able to
Where f
Include the following text in the section description and as a note in Figure 10-9.
“It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping
Interrupt Force Register Low (INTFRCLn) is illustrated as read-only in the figure. However, this register
Change flag clearing mechanism for sources 24-26. They should read as follows:
Write ERR_INT = 1 after reading ERR_INT = 1
Write BOFF_INT = 1 after reading BOFF_INT = 1
Write WAKE_INT = 1 after reading WAKE_INT = 1
BAM bit field description, the first example should read “So, if CSAR0 = 0x0000 and CSMR0[BAM] =
0x0001” instead of “So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008”.
In footnote, remove mention of the SWIACK register, as it is not supported in the global IACK space.
Change last paragraph to: “In addition to the IACK registers within each interrupt controller, there are
global LnIACK registers. A read from one of the global LnIACK registers returns the vector for the highest
priority unmasked interrupt within a level for all interrupt controllers. There is no global SWIACK register.
However, reading the SWIACK register from each interrupt controller returns the vector number of the
highest priority unmasked request within that controller.”
Change SDRAM address lines from A[31:0] to A[23:0].
NOP command entry. Replace “SRAS asserted” with “SDRAM_CS[1:0] asserted”
Add the following note to the DACRn[CBM] field description:
Note: It is important to set CBM according to the location of the command bit.
Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is not supported.
interrupt the processor. Use the peripheral watchdog timer described in Chapter 18 if needing a
watchdog timer to reset the device.
programmed in the interrupt control register 8 (ICR8)...”
level and priority definitions. Failure to program the ICRnx registers in this manner can result in
undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain
in its reset (and disabled) state.”
should be read/write.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
sys(max)
Table B-7. Rev. 2.3 to Rev. 3 Changes (continued)
is the maximum system frequency for the particular MCF5282 device (66MHz or 80MHz)
f
sys
=
f
-------------------------------------------- - f
ref
×
2 MFD
2
(
RFD
+
2
)
;
ref
Description
×
2 MFD
(
+
2
)
≤
f
sys max
(
)
;
f
sys
≤
f
sys max
(
)
Revision History
B-9