MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 440

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

UART Modules
23.4.2.2
The receiver is enabled through its UCRn, as described in
(UCRn).”
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on URXDn, the state of
URXDn is sampled eight times on the edge of the bit time clock starting one-half clock after the transition
(asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If
URXDn is sampled high, start bit is invalid and the search for the valid start bit begins again.
If URXDn remains low, a valid start bit is assumed. The receiver continues sampling the input at one-bit
time intervals at the theoretical center of the bit until the proper number of data bits and parity, if any, is
assembled and one stop bit is detected. Data on the URXDn input is sampled on the rising edge of the
programmed clock source. The lsb is received first. The data then transfers to a receiver holding register
and USRn[RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the
receiver holding register are cleared.
After the stop bit is detected, receiver immediately looks for the next start bit. However, if a non-zero
character is received without a stop bit (framing error) and URXDn remains low for one-half of the bit
period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error,
23-20
USRn[TXRDY]
UCTSn
URTSn
Transmitter
UTXDn
Enabled
internal
module
1
2
3
4
UMR2n[TXRTS] = 1
select
Cn = transmit characters
W = write
UMR2n[TXCTS] = 1
4
3
Receiver
Manually asserted
by
C1
W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
BIT
2
1
-
SET
C1
1
Figure 23-19. Transmitter Timing Diagram
command
C1 in transmission
C2
W
C2
C3
W
break
Start
W
Section 23.3.5, “UART Command Registers
C3
Break
C4 Stop
W
break
W
transmitted
C4
not
C5
W
Freescale Semiconductor
Manually
asserted
C6
W
C6