MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 297

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Chapter 16
DMA Controller Module
This chapter describes the direct memory access (DMA) controller module. It provides an overview of the
module and describes in detail its signals and registers. The latter sections of this chapter describe
operations, features, and supported data transfer modes in detail.
16.1
The DMA controller module provides an efficient way to move blocks of data with minimal processor
interaction. The DMA module, shown in
longword, or 16-byte burst data transfers. Each channel has a dedicated source address register (SARn),
destination address register (DARn), byte count register (BCRn), control register (DCRn), and status
register (DSRn). Transfers are dual address to on-chip devices, such as UART, SDRAM controller, and
GPIOs.
Freescale Semiconductor
Read Data Bus
Overview
The designation “n” is used throughout this section to refer to registers or
signals associated with one of the four identical DMA channels: DMA0,
DMA1, DMA2 or DMA3.
Data Path
Requests
External
Internal
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Bus
Requests
Channel
Write Data Bus
Channel 0
Figure 16-1. DMA Signal Diagram
DAR0
BCR0
DCR0
DSR0
SAR0
Data Path
Control
Channel
Enables
Figure
Control
Channel 1
MUX
BCR1
DCR1
DSR1
SAR1
DAR1
NOTE
Arbitration/
16-1, provides four channels that allow byte, word,
Control
MUX
Channel 2
Channel
Attributes
BCR2
DCR2
DSR2
SAR2
DAR2
Current Master Attributes
System Bus Address
System Bus Size
Channel 3
DCR3
SAR3
DAR3
BCR3
DSR3
Interrupts
Bus Interface
Bus Signals
Registered
16-1