SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 86

• Manufacturer Part Number: SAK-TC1775-L40E BA
• Description: IC MCU 32BIT 40MHZ BGA-329
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1775-L40E BA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SDLM, SSC, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 176
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: ROM
• Ram Size: 73K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.75 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 329-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAKTC1775L40EBA; SP000012965

Preliminary
PLL Parameters
Note: All PLL characteristics defined on this and the next page are guaranteed by design
V
Parameter
Accumulated jitter
VCO frequency range
PLL base frequency
PLL lock-in time
Phase Locked Loop Operation
When PLL operation is enabled and configured (see
clock
frequency. The relation between
causes a jitter of
has its frequency.
The following two formulas define the (absolute) approximate maximum value of jitter
in ns dependent on the K-factor, the system clock frequency
number
With rising number
of
accumulated jitter remains at a constant value. Further, a lower system clock frequency
f
Figure 31
Data Sheet
SYS
SS
P
= 0 V;
results in a higher maximum jitter.
that is defined by the K-factor of the PLL. Beyond this value of
f
characterization.
VCO
for
for
P
P
P
of consecutive
gives an example for the jitter curves with
V
(and with it the system clock
>
<
DD
23.5
23.5
= 2.30 to 2.75 V;
K
f
K
SYS
P
and also of CLKOUT, which is directly derived from
of clock cycles the maximum jitter increases linearly up to a value
f
SYS
periods.
f
T
VCO
D
D
A
N
N
= -40 C to +125 C;
[ns] =
[ns] =
and
Symbol
D
f
f
t
VCO
PLLBASE
L
N
82
f
f
SYS
SYS
) is constantly adjusted to the selected
f
f
is defined by:
SYS
SYS
3.9
min.
150
40
–
[MHz]
[MHz]
91.7
K
Figure 18
= 8.
see
Limit Values
Figure 31
P
K
f
VCO
+ 1.2
max.
200
130
200
and
+ 1.2
f
SYS
= K
Page
in MHz, and the
P
f
f
SYS
the maximum
SYS
V1.2, 2002-05
59), the PLL
Unit
–
MHz
MHz
s
and which
. The PLL
TC1775
D
[1]
[2]
N