SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet
SAK-TC1775-L40E BA
Specifications of SAK-TC1775-L40E BA
SP000012965
Related parts for SAK-TC1775-L40E BA
SAK-TC1775-L40E BA Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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TC1775 Data Sheet Preliminary Revision History: Previous Versions: Page Subjects (major changes since last revision) Changes from V1.1, 2001-08 to V1.2, 2002-05 – Status of data sheet changed from “Advance Information” into “Preliminary” 36 ADC features: example of 10-bit ADC ...
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Preliminary 32-Bit Single-Chip Microcontroller TriCore Family • High Performance 32-bit TriCore CPU with 4-Stage Pipeline – Instruction Cycle Time at 40 MHz CPU Clock • Dual Issue super-scalar implementation – Instruction triple issue • Circular Buffer and bit-reverse ...
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... This ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. The TC1775 is available with the following ordering code: Type Ordering Code SAK-TC1775-L40E Q67121-C2285-A701 P-BGA-329 Data Sheet Package Description 32-Bit Single-Chip ...
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Preliminary Block Diagram Figure 1 TC1775 Block Diagram Data Sheet 0 Port 1 Port Interface FPI OCDS 5 Port 12 Port 11 Port 3 TC1775 2 Port 10 Port V1.2, 2002-05 ...
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Preliminary Logic Symbol TESTMODE CLKOUT HDRST PORST General Control BYPASS CLKSEL Oscillators / PLL JTAG / OCDS OCDSE BRKOUT Digital Circuitry Power Supply V ADC0 / ADC1 Analog Power Supply Figure 2 TC1775 Logic Symbol Data Sheet CLKIN NMI 4 ...
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Preliminary Pin Configuration ...
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Preliminary Table 1 Pin Definitions and Functions Symbol Pin In Out P0 I/O P0.0 N1 I/O P0.1 N4 I/O P0.2 P3 I/O P0.3 P2 I/O P0.4 P1 I/O P0.5 R3 I/O P0.6 R2 I/O P0.7 R4 I/O P0.8 T3 I/O ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P1 I/O P1.0 H2 I/O P1.1 H3 I/O P1.2 J1 I/O P1.3 J4 I/O P1.4 J2 I/O P1.5 J3 I/O P1.6 K1 I/O P1.7 K2 I/O P1.8 L1 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P2 I/O P2.0 AB3 I/O P2.1 AA4 I/O P2.2 Y5 I/O P2.3 AC4 I/O P2.4 AB4 I/O P2.5 AA5 I/O P2.6 AC5 I/O P2.7 AB5 I/O P2.8 AA6 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P3 I/O P3.0 AB8 I/O P3.1 AA8 I/O P3.2 AC9 I/O P3.3 Y9 I/O P3.4 AB9 I/O P3.5 AA9 I/O P3.6 AC10 I/O P3.7 AB10 I/O P3.8 AA10 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P4 I/O 1) P4.0 V3 I/O 1) P4.1 W2 I P4.4 Y2 I/O 1) P4.5 Y1 I/O 1) P4.6 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P5 I/O P5.0 AB13 O P5.1 AA13 O P5.2 AC13 O P5.3 Y13 O P5.4 AA14 O P5.5 AB14 O P5.6 AC14 O P5.7 AA15 O P5.8 Y15 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P6.8 C6 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P8 I/O P8.0 U23 I/O P8.1 U20 I/O P8.2 U22 I/O P8.3 U21 I/O P8.4 T23 I/O P8.5 T22 I/O P8.6 T21 I/O P8.7 R23 I/O P8.8 R20 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P10 I/O P10.0 H21 I/O P10.1 H22 I/O P10.2 H23 I/O P10.3 G21 I/O P10.4 G22 I/O P10.5 G20 I/O P10.6 G23 I/O P10.7 F22 I/O P10.8 F23 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P12 I/O P12.0 D13 O P12.1 A13 O P12.2 B13 O P12.3 C13 O P12.4 C12 O P12.5 A12 O P12.6 B12 I P12.7 B11 I P12.8 C11 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P13 I/O P13.0 B19 I/O P13.1 C18 I/O P13.2 A18 I/O I/O P13.3 B18 I/O O P13.4 A17 I/O I/O P13.5 D17 I/O O P13.6 B17 I/O I/O ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out BYPASS W22 I CFG0 Y23 I CFG1 Y22 I CFG2 W21 I CFG3 W23 I 3) TRST AA19 I 3) TCK AB19 I 4) TDI AC19 I TDO ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out 4) HDRST W20 I/O 5) PORST Y21 I CLKIN T1 I CLKOUT R1 O TEST AB23 I 4) MODE XTAL1 AC23 I XTAL2 AC22 O XTAL3 AB21 I ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out V AC21 – DDOSC V AA21 – SSOSC V AA22 – DDPLL V AA23 – SSPLL V F4, Y6, – SS V20, D18, K10 to K14, L10 to ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out V H4 – DDP05 Y12 V D8 – DDP813 D12 D16 H20 M20 T20 V AC17, – DDSRAM AB18 V B14 – DDSB V A1 ...
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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out N.C.1 AB15, – D10, Y14 N.C.2 AB22, – C14, K3, AC3, L4, D21, Y16 1) After reset, an internal pull-up device is enabled for this pin. 2) After ...
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Preliminary Parallel Ports The TC1775 has 196 digital input/output port lines, which are organized into twelve parallel 16-bit ports, Port 0 to Port 5 with 2.5 V nominal voltage (pin class B), and Port 8 to Port 13 with 3.0 ...
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Preliminary Serial Interfaces The TC1775 includes six serial peripheral interface units: – Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1) – Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) – One TwinCAN Interface – One J1850 Serial Data Link Interface (SDLM) ...
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Preliminary Each ASC module, ASC0 and ASC1, communicates with the external world via two pairs of two I/O lines each. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. ...
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Preliminary High-Speed Synchronous Serial Interfaces Figure 6 shows a global view of the functional blocks of the two High-Speed Synchronous Serial interfaces SSC0 and SSC1 ntro ...
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Preliminary Features: • Master and slave mode operation – Full-duplex or half-duplex operation • Flexible data format – Programmable number of data bits bit – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: ...
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Preliminary TwinCAN Interface Figure 7 shows a global view of the functional blocks of the TwinCAN module inC rne ntro l ...
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Preliminary The bit timings for both CAN nodes are derived from the peripheral clock ( programmable data rate of 1 Mbit/s. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features: ...
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Preliminary Serial Data Link Interface Figure 8 shows a global view of the functional blocks of the Serial Data Link Interface (SDLM ntro res s D ...
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Preliminary Data Link Operation Features: • 11-byte transmit buffer • Double buffered 11-byte receive buffer • Support of In-Frame Response (IFR) types • Advanced interrupt handling for RX, TX, and error conditions • All interrupt sources can ...
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Preliminary Timer Units The TC1775 includes two timer units: – General Purpose Timer Unit (GPTU) – General Purpose Timer Array (GPTA) General Purpose Timer Unit Figure 9 shows a global view of all functional blocks of the General Purpose Timer ...
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Preliminary Features of T0 and T1: • Each timer has a dedicated 32-bit reload register with automatic reload on overflow • Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers • Overflow signals can ...
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Preliminary General Purpose Timer Array Figure 10 shows a global block diagram of the General Purpose Timer Array (GPTA) implementation trol P res dre ss ...
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Preliminary The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units (PDL) decode ...
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Preliminary f – maximum resolution GPTA f – /2 maximum input signal frequency GPTA • Digital Phase Locked Loop (PLL): – One unit – Arbitrary multiplication factor between 1 and 65535 f – maximum resolution GPTA f – /2 maximum ...
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Preliminary Analog Digital Converters The two on-chip Analog-to-Digital Converter (ADC) modules of the TC1775 offer 8-bit, 10-bit, or 12-bit resolution including sample-and-hold functionality. The A/D converters operate using the method of the successive approximation. A multiplexer selects among up to ...
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Preliminary ntro res terru pt S ...
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Preliminary On-Chip Memories The memory system of the TC1775 provides the following memories: • Program Memory Unit (PMU) with – 8 Kbytes Boot ROM (BROM) – 32 Kbytes Code Scratch-Pad RAM (SPRAM) – 1 Kbyte Instruction Cache (ICACHE) • Data ...
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Preliminary Address Map Table 2 defines the specific segment oriented address blocks of the TC1775 with its address range, size, and PMU/DMU access view. of memory segment 15 which includes the on-chip peripheral units. Table 2 TC1775 Block Address Map ...
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Preliminary Table 2 TC1775 Block Address Map (cont’d) Seg- Address Size ment Range D000 0000 – D000 7FFF H D000 8000 – D000 9FFF H D000 A000 – D000 BFFF H ...
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Preliminary Table 2 TC1775 Block Address Map (cont’d) Seg- Address Size ment Range F000 0000 – F000 3EFF H F000 3F00 – 256 B H F000 3FFF H F000 4000 – – H F000 FFFF H F001 ...
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Preliminary Table 3 Block Address Map of Segment 15 Symbol Description SCU System Control Unit RTC Real Time Clock BCU Bus Control Unit STM System Timer OCDS On-Chip Debug Support EBU External Bus Unit – Reserved GPTU General Purpose Timer ...
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Preliminary Table 3 Block Address Map of Segment 15 (cont’d) Symbol Description P10 Port 10 P11 Port 11 P12 Port 12 P13 Port 13 – Reserved PCP PCP Registers Reserved PCP Data Memory (PRAM) Reserved PCP Code Memory (PCODE) – ...
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Preliminary Memory Protection System The TC1775 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It ...
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Preliminary On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1775, such as the CPU and on-chip peripheral components. The FPI Bus also interconnects the TC1775 to external components by way of the External Bus Controller Unit ...
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Preliminary External Bus Unit The External Bus Unit (EBU) of the TC1775 is the interface between external memories and peripheral units and the internal memories and peripheral units. The basic structure of the EBU is shown in Figure w ith ...
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Preliminary Peripheral Control Processor The Peripheral Control Processor (PCP) performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered ...
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Preliminary I-Interfa Figure 13 PCP Block Diagram Table 4 PCP Instruction Set Overview Instruction Group Description DMA ...
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Preliminary System Timer The STM within the TC1775 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: • Free-running 56-bit counter • All 56 bits can be read synchronously ...
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Preliminary Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1775 in a user-specified time period. When ...
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Preliminary • Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. Real Time Clock Figure 15 shows a global view ...
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Preliminary System Control Unit The System Control Unit (SCU) of the TC1775 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU ...
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Preliminary Interrupt System An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called “Service Providers”. Interrupt requests are called “Service Requests” rather than “Interrupt Requests” in this document because ...
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Preliminary S erv stors ...
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Preliminary Boot Options The TC1775 booting schemes provides a number of different boot options for the start of code execution. Table 5 Table 5 Boot Selections OCDSE BRKIN CFG [ ...
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Preliminary Power Management System The TC1775 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: • Run Mode ...
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Preliminary On-Chip Debug Support The On-Chip Debug Support of the TC1775 consists of four building blocks: • OCDS module in the TriCore CPU – On-chip breakpoint hardware – Support of an external break signal • OCDS module in the PCP ...
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Preliminary Clock Generation Unit The Clock Generation Unit (CGU) in the TC1775, shown in oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL ...
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Preliminary PLL Operation f The clock of the PLL has a frequency which is a multiple of the externally applied VCO f clock . The factor for this is controlled through the value N applied to the divider in OSC ...
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Preliminary Recommended Oscillator Circuits Figure 19 Oscillator Circuitries For the main oscillator of the TC1775 the following external passive components are recommended: – Crystal: max. 16 MHz C C – ...
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Preliminary Power Supply Figure 20 shows the TC1775’s power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. Also the operation margin is improved in ...
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Preliminary Ports Power Supply The TC1775’s port power supply concept is shown in the External Bus Unit (EBU) are in a separate power supply group for 2.5 V nominal operating voltage. The general purpose input/outputs (GPIOs) except the EBU provide ...
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Preliminary Identification Register Values Table 9 TC1775 Identification Registers Short Name PMU_ID DMU_ID SCU_ID MANID CHIPID RTID RTC_ID BCU_ID STM_ID JPD_ID EBU_ID GPTU_ID ASC0_ID ASC1_ID SSC0_ID SSC1_ID GPTA_ID ADC0_ID ADC1_ID SDLM_ID PCP_ID CAN_ID CPU_ID Data Sheet Address C7FF FF08 H ...
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Preliminary Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1775 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked ...
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Preliminary Absolute Maximum Ratings Parameter Ambient temperature Storage temperature Junction temperature Voltage on Class A power supply V pins with respect to SS Voltage on Class B and C power supply pins with respect to Voltage on power supply pins ...
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Preliminary Package Parameters (P-BGA-329) Parameter Power dissipation Thermal resistance Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1775. All parameters specified in the following table refer to these operating conditions, ...
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Preliminary 1) Digital supply voltages applied to the TC1775 must be static regulated voltages which allow a typical voltage swing of 10 This specification is applicable for the power supply pins order to minimize ...
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Preliminary DC Characteristics Input/Output DC-Characteristics - +125 Parameter Symbol V Class A Pins ( = 3.0 to 5.25 V) DDP813 V 2) Output low voltage ...
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Preliminary Input/Output DC-Characteristics (cont’ - +125 Parameter Symbol V Class B Pins ( = 2.30 to 2.75 V) DDP05 V Output low voltage OL V Output high voltage ...
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Preliminary Input/Output DC-Characteristics (cont’ - +125 Parameter Symbol I Constant short-circuit SCBDcons current Constant back-drive current (per digital pin Pin capacitance IO (Digital I/O) V Class ...
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Preliminary Pull-Up/Pull-Down Characteristics Pull-up 700 µA I 600 Best Case 500 400 Nominal 300 200 Worst Case 100 Figure 22 Pull-Up/Pull-Down Characteristics of Class A Pins Data Sheet 700 µA I 600 500 400 300 200 ...
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Preliminary Pull-up 250 µA I Best Case 200 150 Nominal 100 Worst Case 0.5 1 Figure 23 Pull-Up/Pull-Down Characteristics of Class B Pins Note: The pull-up/pull-down characteristics as shown in guaranteed by design characterization. Data Sheet 250 ...
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Preliminary AD Converter Characteristics - +125 C; A Parameter Symbol V Analog supply voltages Analog ground voltage V Analog reference voltage V Analog reference ground V Analog input voltage range f Internal ...
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Preliminary AD Converter Characteristics (cont’ - +125 C; A Parameter Symbol k Overload coupling A 10) factor I Input leakage current at OZ1 analog inputs I Input leakage current at OZ2 V V and AGND ...
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Preliminary 10) The overload coupling factor ( the resulting leakage current ( Thus under overload conditions an additional error leakage voltage ( analog input pin due to the resistance of the analog input source ( See also section 7.1.6 “Error ...
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Preliminary A/D Converter Module Peripheral f Clock Divider ADC (1:1) to (1:8) CON.PCD Arbiter (1:20) Figure 25 ADC Clock Circuit f Note: The frequency of ADC bit field ADCx_CLC.RMC. Oscillator Pins (Class C Pins - ...
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Preliminary Power Supply Current +125 C; A Parameter Active mode supply current Idle mode supply current Sleep mode supply current Deep sleep mode supply current Stand-by pin power supply current 1) Parameters in this column ...
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Preliminary AC Characteristics Output Rise/Fall Times Class A drivers (GPIO/peripheral ports 8 to 13): Class B drivers (Bus interface ports +125 C, unless otherwise noted; A Parameter Symbol Class A Pins t ...
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Preliminary Testing Waveforms +125 C; Frequency: max. 40 MHz Class A Pins: = 3.0 to 5.25 V; DDP813 V IHmin V OHmin V OLmax V ILmax AC inputs during testing are driven with ...
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Preliminary Input Clock Timing V = 2.30 to 2.75 V; DDOSC Parameter Oscillator clock frequency Input clock frequency driving at XTAL1 Input clock high time Input clock low time Input clock rise time Input clock fall time Input Clock V ...
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Preliminary CLKOUT Timing 2. DDP05 Parameter Clock period Clock high time Clock low time Clock rise time Clock fall time Clock duty cycle /( + 5 5 ...
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Preliminary PLL Parameters Note: All PLL characteristics defined on this and the next page are guaranteed by design characterization 2. Parameter Accumulated jitter VCO frequency range PLL base frequency ...
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Preliminary ±2 ±1.6 ±1.4 ±1.2 ±1 Max. jitter Number of consecutive K-divider of PLL Figure 31 Approximated Maximum Accumulated PLL Jitter (for Note: For safe ...
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Preliminary EBU Demultiplexed Timing 2. DDP05 Parameter Output delay from CLKOUT Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Data valid after CLKOUT 2) Data setup ...
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Preliminary CLKOUT CLKIN t 10 A[25:0] CODE SVM ADV t 10 CSx RD RD/WR D[31:0] Normal Sampling D[31:0] Early Sampling t 10 BC[3:0] 1) Early sampling for D[31:0] not available in TC1775 BA11 step. Figure 32 EBU Demultiplexed Read Timing ...
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Preliminary ...
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Preliminary EBU Multiplexed Timing 2. DDP05 Parameter Output delay from CLKOUT Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Address and data valid after CLKOUT 1) ...
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Preliminary 1: ...
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Preliminary WAIT Timing (FPI Bus to external Memory 2. DDP05 Parameter WAIT setup to CLKOUT WAIT hold from CLKOUT WAIT setup to CLKOUT WAIT hold from CLKOUT 1) Guaranteed by ...
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Preliminary EBU Burst Mode Timing 2. DDP05 Parameter Output delay from CLKIN Data setup to CLKIN Data hold from CLKIN 1) Guaranteed by design characterization ...
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Preliminary EBU Arbitration Signal Timing 2. DDP05 Parameter Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT CLKOUT HLDA Output BREQ Output CLKOUT HOLD Input HLDA Input ...
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Preliminary EBU External Access Timing 2. DDP05 Parameter CSFPI, BC[3:0], A[23:2] setup before RD or RD/WR Data valid after RD WAIT active after RD RD/WAIT float after RD Data setup ...
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Preliminary R ead Tim ing [31 : rite Tim ing A [2 3:2] ...
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Preliminary Port 5 (Trace Port) Timing This timing is applicable for Port 5 when CPU or PCP trace mode is enabled (SCU_CON.ETEN = 1 2. DDP05 Parameter Port 5 lines ...
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Preliminary SSC Master Mode Timing 4 DDP813 Parameter SCLK/MTSR low/high from CLKOUT MRST setup to SLCK rising/falling edge MRST hold from SLCK rising/falling edge 1) This parameter is valid for ...
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Preliminary Package Outlines P-BGA-329 (Plastic Ball Grid Array Package) 1.95 x 45˚ You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 22 x ...
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