SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 33

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SAK-TC1775-L40E BA

Manufacturer Part Number
SAK-TC1775-L40E BA
Description
IC MCU 32BIT 40MHZ BGA-329
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet

Specifications of SAK-TC1775-L40E BA

Core Processor
TriCore
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SDLM, SSC, UART/USART
Peripherals
POR, WDT
Number Of I /o
176
Program Memory Size
8KB (8K x 8)
Program Memory Type
ROM
Ram Size
73K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.75 V
Data Converters
A/D 32x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
329-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
SAKTC1775L40EBA
SP000012965
Preliminary
Serial Data Link Interface
Figure 8
(SDLM).
Figure 8
The SDLM module communicates with the external world via two I/O lines located at
Port 12, the J1850 bus. The RXD line is the receive data input signal and TXD is the
transmit data output signal.
The Serial Data Link module (SDLM) provides serial communication to a J1850 based
serial bus. J1850 bus transceivers must be implemented externally in a system. The
SDLM module conforms to the SAE Class B J1850 Specification and is compatible to
Class 2 protocol.
General SDLM Features:
• Compliant to SAE Class B J1850 Specification
• Full support of GM Class 2 protocol
• Variable Pulse Width (VPW) format with 10.4 kbit/s
• High speed receive/transmit 4x mode with 41.6 kbit/s
• Digital noise filter
• Support of single byte headers or consolidated headers
• CRC generation and check
• Support of Block Mode for receive and transmit
Data Sheet
D e co de r
A d d res s
In terru pt
C o ntro l
C o ntro l
C lo ck
shows a global view of the functional blocks of the Serial Data Link Interface
General Block Diagram of the SDLM Interface
f
S D L M
(K e rne l)
M o du le
S D LM
29
R X D
T X D
C o n tro l
P o rt
P 12 .1 0 /
R X J1 8 50
P 12 .1 1 /
T X J 18 50
M C B 04570
V1.2, 2002-05
TC1775

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