SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 21

• Manufacturer Part Number: SAK-TC1775-L40E BA
• Description: IC MCU 32BIT 40MHZ BGA-329
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1775-L40E BA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SDLM, SSC, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 176
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: ROM
• Ram Size: 73K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.75 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 329-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAKTC1775L40EBA; SP000012965

Preliminary
Table 1
Symbol
BYPASS
CFG0
CFG1
CFG2
CFG3
TRST
TCK
TDI
TDO
TMS
OCDSE
BRKIN
BRKOUT AC18
NMI
Data Sheet
4)
4)
3)
4)
3)
4)
4)
Pin
W22
Y23
Y22
W21
W23
AA19
AB19
AC19
AA18
AB20
Y19
AC20
Y20
Pin Definitions and Functions (cont’d)
In
Out
I
I
I
I
I
I
I
I
O
I
I
I
O
I
Functions
PLL Bypass Control Input
BYPASS is used for direct drive mode operation of the clock
circuitry. This pin is sampled during power-on reset
(PORST = low). Its level is latched into the PLL Clock
Control Register PLL_CLC. The combination BYPASS = 1
and CLKSEL[2:0] = 000
Operation Configuration Inputs
The configuration inputs define the boot options of the
TC1775 after a hardware reset operation.
JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
JTAG Module Clock Input
JTAG Module Serial Data Input
JTAG Module Serial Data Output
JTAG Module State Machine Control Input
OCDS Enable Input
A low level on this pin during power-on reset (PORST = low)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
OCDS Break Output
A low level on this pin indicates that a programmable OCDS
event has occurred.
Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
17
B
during power-on reset is reserved.
V1.2, 2002-05
TC1775