SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 31

• Manufacturer Part Number: SAK-TC1775-L40E BA
• Description: IC MCU 32BIT 40MHZ BGA-329
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1775-L40E BA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SDLM, SSC, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 176
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: ROM
• Ram Size: 73K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.75 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 329-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAKTC1775L40EBA; SP000012965

Preliminary
TwinCAN Interface
Figure 7
Figure 7
The TwinCAN module has four I/O lines located at Port 13. The TwinCAN module is
further supplied by a clock control, interrupt control, address decoding, and port control
logic.
The TwinCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames are handled in accordance to CAN specification V2.0 part B (active).
Each of the two Full-CAN interfaces can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic
handling and to minimize the CPU load. The flexible combination of Full-CAN
functionality and the FIFO architecture reduces the efforts to fulfill the real-time
requirements of complex embedded control applications. Improved CAN bus monitoring
functionality as well as the increased number of message objects permit precise and
convenient CAN bus traffic handling.
Depending on the application, each of the thirty-two message objects can be individually
assigned to one of the two CAN nodes. Gateway functionality allows automatic data
exchange between two separate CAN bus systems to reduce CPU load and improve the
real time behavior of the entire system.
Data Sheet
A d d res s
D e co de r
In terru pt
C o ntro l
C o ntro l
C lo ck
shows a global view of the functional blocks of the TwinCAN module.
f
S R 0
S R 1
S R 2
S R 3
S R 4
S R 5
S R 6
S R 7
C A N
General Block Diagram of the TwinCAN Module
In terru pt
C o ntro l
Tw inC A N M od u le K e rne l
P roc es so r
B its tre a m
M es sa ge
B u ffe rs
C o n tro l
Tim in g
H a nd lin g
C o ntrol
E rro r
27
T X D C 0
T X D C 1
R X D C 0
R X D C 1
C o n tro l
P o rt
V1.2, 2002-05
P 13 .13 /
T X D C A N 0
P 13 .12 /
R X D C A N 0
P 13 .15 /
T X D C A N 1
P 13 .14 /
R X D C A N 1
M C B 04674
TC1775