HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 426

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
Legend:
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of an External Clock Source:
• When an external clock source is used for the serial clock, after updates TDR, allow an
Rev.4.00 Aug. 20, 2007 Page 380 of 638
REJ09B0395-0400
Note: In operation with an external clock source, be sure that t >4 states.
inversion of at least five system clock (φ) cycles before input of the serial clock to start
transmitting. If the serial clock is input within four states of the TDR update, a malfunction
may occur. (See figure 12.22)
SCK
TDRE
M = (0.5 −
M = (0.5 −
= 46.875%
t
Figure 12.22 Example of Synchronous Transmission
2 × 16
2N
D0
1
1
) − (L − 0.5) F −
) × 100%
D1
D2
D − 0.5
N
D3
(1 + F) × 100%
D4
D5
. . . . . . . . (1)
. . . . . . . . (2)
D6
D7