HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 75
HD6473837H
Manufacturer Part Number
HD6473837H
Description
IC H8 MCU OTP 60K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837H
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: When a BCLR instruction is executed on PCR3 of port 3
In this example, the port 3 control register PCR3 is accessed by a BCLR instruction.
As in the examples above, P3
high-level signal at P3
signals. In this example, the BCLR instruction is used to change pin P3
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
Input/output
Pin state
PCR3
PDR3
[B: BCLR instruction executed]
[C: After executing BCLR]
Input/output
Pin state
PCR3
PDR3
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
58
BCLR
#0
P3
Input
Low
level
0
1
P3
Output
Low
level
1
1
,
7
7
6
. The remaining pins, P3
@PCR3
P3
Input
High
level
0
0
P3
Output
High
level
1
0
7
6
6
and P3
6
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
The BCLR instruction is executed designating PCR3.
are input pins, with a low-level signal input at P3
5
5
5
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
to P3
4
4
0
, are output pins that output low-level
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
3
3
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
0
2
2
to an input port. It is
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
1
1
7
P3
Output
Low
level
1
0
P3
Input
High
level
0
0
and a
0
0
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