HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 235
HD6473837H
Manufacturer Part Number
HD6473837H
Description
IC H8 MCU OTP 60K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837H
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated.
Count Timing: TCG is incremented by input pulses from an internal clock. TMG bits CKS1 and
CKS0 select one of four internal clocks ( /64, /32, /2,
clock ( ) or the watch clock (
Timing of Internal Input Capture Signals:
218
External input
capture signal
Internal input
capture signal F
Internal input
capture signal R
Interval timer operation
Timer G functions as an interval timer when bit TMIG is cleared to 0 in PMR1. Following a
reset, TCG starts counting cycles of the /64 internal clock. This is one of four internal clock
sources that can be selected by bits CKS1 and CKS0 of TMG. TCG counts up according to the
selected clock source. When it overflows from H'FF to H'00, bit OVFL of TMG is set to 1. If
bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also
set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts.
Timing with noise canceller function disabled
Separate internal input capture signals are generated from the rising and falling edges of the
external input signal.
Figure 9.11 shows the timing of these signals.
Timing with noise canceller function enabled
When input capture noise cancelling is enabled, the external input capture signal is routed via
the noise canceller circuit, so the internal signals are delayed from the input edge by five
sampling clock cycles. Figure 9.12 shows the timing.
Figure 9.11 Input Capture Signal Timing (Noise Canceller Function Disabled)
W
).
W
/2) derived by dividing the system
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