HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 208
HD6473837H
Manufacturer Part Number
HD6473837H
Description
IC H8 MCU OTP 60K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837H
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bits 4 and 3—Reserved Bits: Bits 4 and 3 are reserved; they are always read as 1, and cannot be
modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0): Bits 2 to 0 select the clock input to TCC. For
external clock counting, either the rising or falling edge can be selected.
Bit 2: TMC2
0
1
Note: * The edge of the external event signal is selected by bit IEG2 in the IRQ edge select register
Timer Counter C (TCC)
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.
TCC is allocated to the same address as timer load register C (TLC).
Upon reset, TCC is initialized to H'00.
Bit
Initial value
Read/Write
(IEGR). See 3.3.2, for details on the IRQ edge select register. Be sure to set bit IRQ2 in
port mode register 1 (PMR1) to 1 before setting bits TMC2 to TMC0 to 111.
Bit 1: TMC1
0
1
0
1
TCC7
R
7
0
TCC6
R
6
0
Bit 0: TMC0
0
1
0
1
0
1
0
1
TCC5
R
5
0
TCC4
R
4
0
Description
Internal clock: /8192
Internal clock: /2048
Internal clock: /512
Internal clock: /64
Internal clock: /16
Internal clock: /4
Internal clock:
External event (TMIC): rising or falling edge*
TCC3
R
3
0
W
/4
TCC2
R
2
0
TCC1
R
1
0
(initial value)
TCC0
R
0
0
191
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