HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 274
HD6473837H
Manufacturer Part Number
HD6473837H
Description
IC H8 MCU OTP 60K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837H
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit 2—Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end
interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2: TEIE
0
1
Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit
Bits 1 and 0—Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable
or disable clock output at pin SCK
pin SCK
Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal
clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock
(CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits
CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR).
See table 10.9 in 10.4.3, Operation, for details on clock source selection.
Bit 1: CKE1
0
0
1
1
Notes: 1. Initial value
Serial Status Register (SSR)
Note: * Only 0 can be written for flag clearing.
Bit
Initial value
Read/Write
end bit (TEND) to 0, or by clearing bit TEIE to 0.
2. A clock is output with the same frequency as the bit rate.
3. Input a clock with a frequency 16 times the bit rate.
3
is a general I/O port, a clock output pin, or a clock input pin.
Bit 0: CKE0
0
1
0
1
R/(W)*
TDRE
Description
Transmit end interrupt (TEI) disabled
Transmit end interrupt (TEI) enabled*
7
1
R/(W)*
RDRF
6
0
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
3
. The combination of bits CKE1 and CKE0 determines whether
R/(W)*
OER
5
0
R/(W)*
FER
4
0
Clock Source
Internal clock
Internal clock
Internal clock
Reserved
External clock
External clock
Reserved
Reserved
R/(W)*
PER
3
0
TEND
R
2
1
SCK
I/O port
Serial clock output
Clock output
Reserved
Clock input
Serial clock input
Reserved
Reserved
MPBR
3
R
1
0
Pin Function
*
1
(initial value)
*
3
*
MPBT
2
R/W
0
0
257
*
1
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