HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 255
HD6473837H
Manufacturer Part Number
HD6473837H
Description
IC H8 MCU OTP 60K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837H
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 select one of seven internal clock
sources or an external clock as the transfer clock.
Bit 2:
CKS2
0
1
Serial Control/Status Register 2 (SCSR2)
Note: * Only a write of 0 for flag clearing is possible.
SCSR2 is an 8-bit register indicating SCI2 operation status and error status.
Upon reset, SCSR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4—Extended Data Bit (SOL): Bit 4 sets the SO
transmitted data output at the SO
the value of the last bit of transmitted data. The SO
before or after a transmission. The SOL bit setting remains valid only until the start of the next
transmission. To control the level of the SO
the SOL bit at the end of each transmission. Note that if the STF bit is cleared to 0 to terminate a
transmission in progress, the transmitted data will be modified when the bit is cleared.
238
Bit
Initial value
Read/Write
Bit 1:
CKS1
0
1
0
1
Bit 0:
CKS0
0
1
0
1
0
1
0
1
—
—
7
1
Pin SCK
SCK
SCK
2
2
—
—
6
1
output Prescaler S
input
2
pin. After completion of a transmission, SO
2
Clock
Source
External
clock
—
—
5
1
2
pin after transmission ends, it is necessary to write to
SOL
R/W
2
4
0
output can be changed by writing to SOL
2
output level. When read, SOL returns the
Prescaler
Division
—
/256 (initial value) 51.2 µs
/64
/32
/16
/8
/4
/2
R/(W)*
ORER
3
0
R/(W)*
WT
2
0
Serial Clock Cycle
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
—
= 5 MHz
2
continues to output
R/(W)*
ABT
1
0
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
= 2.5 MHz
R/W
STF
0
0
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