C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 228

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
228
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF2H
R/W
Bit7
TF2H: Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will
occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is enabled, set-
ting this bit causes the CPU to vector to the Timer 2 interrupt service routine. TF2H is not automati-
cally cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is set, an
interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L will set when
the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hard-
ware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are
enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
T2SOF: Timer 2 Start-Of-Frame Capture Enable
0: SOF Capture disabled.
1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 2 registers
(TMR2H and TMR2L) are latched into the Timer 2 reload registers (TMR2RLH and TMR2RLH),
and a Timer 2 interrupt is generated (if enabled).
T2SPLIT: Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only; TMR2L is
always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit selects the
external oscillator clock source for both timer bytes. However, the Timer 2 Clock Select bits (T2MH
and T2ML in register CKCON) may still be used to select between the external clock and the system
clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator
source divided by 8 is synchronized with the system clock.
TF2L
R/W
Bit6
Figure 19.15. TMR2CN: Timer 2 Control Register
TF2LEN
R/W
Bit5
T2SOF
R/W
Bit4
T2SPLIT
Rev. 1.1
R/W
Bit3
TR2
R/W
Bit2
R/W
Bit1
-
(bit addressable)
T2XCLK
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC8