C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 147
![IC 8051 MCU 16K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F321R
Manufacturer Part Number
C8051F321R
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet
1.C8051F320R.pdf
(256 pages)
Specifications of C8051F321R
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1067-2
- Current page: 147 of 256
- Download datasheet (4Mb)
Bits7:
Bit6:
Bits5-0:
BUSY
R/W
Bit7
BUSY: USB0 Register Read Busy Flag
This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate
a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The target address
and BUSY bit may be written in the same write to USB0ADR. After BUSY is set to ‘1’, hardware
will clear BUSY when the targeted register data is ready in the USB0DAT register. Software should
check BUSY for ‘0’ before writing to USB0DAT.
Write:
0: No effect.
1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits.
Read:
0: USB0DAT register data is valid.
1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid.
AUTORD: USB0 Register Auto-read Flag
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software reads USB0DAT
(USBADDR bits will not be changed).
USBADDR: USB0 Indirect Register Address
These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 15.2 lists the
USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the regis-
ter indicated by the USBADDR bits.
AUTORD
R/W
Bit6
Figure 15.4. USB0ADR: USB0 Indirect Address Register
R/W
Bit5
R/W
Bit4
R/W
Bit3
USBADDR
Rev. 1.1
R/W
Bit2
R/W
Bit1
C8051F320/1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x96
147
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