C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 164

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
164
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SSUEND
R/W
Bit7
SSUEND: Serviced Setup End
Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware
clears the SUEND bit when software writes ‘1’ to SSUEND.
Read: This bit always reads ‘0’.
SOPRDY: Serviced OPRDY
Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The OPRDY
bit will be cleared by a write of ‘1’ to SOPRDY.
Read: This bit always reads ‘0’.
SDSTL: Send Stall
Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition, unex-
pected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL handshake is trans-
mitted.
SUEND: Setup End
Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has written ‘1’
to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to SSUEND.
DATAEND: Data End
Software should write ‘1’ to this bit:
1. When writing ‘1’ to INPRDY for the last outgoing data packet.
2. When writing ‘1’ to INPRDY for a zero-length data packet.
3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be cleared
by software.
INPRDY: IN Packet Ready
Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for transmit.
Hardware clears this bit and generates an interrupt under either of the following conditions:
1. The packet is transmitted.
2. The packet is overwritten by an incoming SETUP packet.
3. The packet is overwritten by an incoming OUT packet.
OPRDY: OUT Packet Ready
Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This
bit is cleared only when software writes ‘1’ to the SOPRDY bit.
SOPRDY
Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register)
R/W
Bit6
SDSTL
R/W
Bit5
SUEND DATAEND
Bit4
R
Rev. 1.1
R/W
Bit3
STSTL
R/W
Bit2
INPRDY
R/W
Bit1
OPRDY
Bit0
R
USB Address:
00000000
Reset Value
0x11