C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 188

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
16.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START
condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case
the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the
SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received,
ACKRQ is set to ‘1’ and an interrupt is generated. Software must write the ACK bit (SMB0CN.1) to define the out-
going acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK).
Software should write a ‘0’ to the ACK bit after the last byte is received, to transmit a NACK. The interface exits
Master Receiver Mode after the STO bit is set and a STOP is generated. Note that the interface will switch to Master
Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 16.9 shows a typical Master
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the
‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
188
Interrupt
S
Figure 16.9. Typical Master Receiver Sequence
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
R
Interrupt
A
Data Byte
Rev. 1.1
Interrupt
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
N
P