C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 204
C8051F321R
Manufacturer Part Number
C8051F321R
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet
1.C8051F320R.pdf
(256 pages)
Specifications of C8051F321R
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1067-2
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C8051F320/1
18.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
18.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an
input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master,
MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode.
18.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an
output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a
high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is
not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register.
18.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchro-
nize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when
operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire
slave mode.
18.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the
SPI0CN register. There are three possible modes that can be selected with these bits:
See Figure 18.2, Figure 18.3, and Figure 18.4 for typical connection diagrams of the various operational modes. Note
that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the
NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device.
See Section
204
1.
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is
present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point commu-
nication between a master and one slave.
2.
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a
1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can
be used on the same SPI bus.
3.
put. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should
only be used when operating SPI0 as a master device.
“14. Port
NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an out-
Input/Output” on page
127
for general purpose port I/O and crossbar information.
Rev. 1.1
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